A low-power, high-speed, 9-channel germanium-silicon electro-absorption modulator array integrated with digital CMOS driver and wavelength multiplexer.

We demonstrate the first germanium-silicon C-band electro-absorption based waveguide modulator array and echelle-grating-based silicon wavelength multiplexer integrated with a digital CMOS driver circuit. A 9-channel, 10Gbps SiGe electro-absorption wavelength-multiplexed modulator array consumed a power of 5.8mW per channel while being modulated at 10.25Gbps by 40nm CMOS drivers delivering peak-to-peak voltage swings of 2V, achieving a modulation energy-efficiency of ~570fJ/bit including drivers. Performance up to 25Gbps on a single-channel SiGe modulator and CMOS driver is also reported.

Power-efficient III-V/silicon external cavity DBR lasers.

We report the design and characterization of external-cavity DBR lasers built with a III-V-semiconductor reflective-SOA with spot-size converter edge-coupled to SOI waveguides containing Bragg grating mirrors. The un-cooled lasers have wall-plug-efficiencies of up to 9.5% at powers of 6 mW. The lasers are suitable for making power efficient, hybrid WDM transmitters in a CMOS-compatible SOI optical platform.

Wide bandwidth, low loss 1 by 4 wavelength division multiplexer on silicon for optical interconnects.

We demonstrate an add/drop filter based on coupled vertical gratings on silicon. Tailoring of the channel bandwidth and wavelength is experimentally demonstrated. The concept is extended to implement a 1 by 4 wavelength division multiplexer with 6 nm channel separation, 3 nm bandwidth, a flat top response with < 0.8 dB ripple within the 3 dB passband, 1 dB insertion loss and 16 dB crosstalk suppression. The device is ultracompact, having a footprint < 2 X 10(-9)/2.

PAM-4 Signaling over VCSELs with 0.13microm CMOS Chip Technology.

We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13microm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM-4 can match or even improve performance over binary signaling under conditions of a bandwidth limited, 100meter multi-mode optical link at 5Gbps. We present the first sensitivity measurements for optical PAM-4 and compare it with binary signaling. Measured benefits are reconciled with information theory predictions.

Automated design of integrated circuits with area-distributed input-output pads.

We present a method for automating the creation of complementary-metal-oxide-semiconductor (CMOS) integrated circuits that successfully utilizes a large number of area-distributed pads for input-output communication. This method uses Duet Technologies' epoch computer-aided-design tool for automated placement and routing of CMOS circuitry, given a schematic netlist as an input. The novelty of this approach is that it uses Duet Technologies' eggo program to place and route area-pad signals. To verify this methodology, it is applied to the design of a digital signal-processing circuit, with 200 optical area-pad input-outputs and 44 perimeter-pad input-outputs, that is being fabricated with Bell Labs 1997 CMOS-multiple-quantum-well foundry. The layout results are as good as or better than the results obtained by manual layout.

Optoelectronic-VLSI packaging with polarization-selective computer-generated holograms.

We present what is believed to be the first packaged module incorporating polarization-based beam-forming optics integrated with an optoelectronic-VLSI device. The chip has multiple quantum-well modulators and detectors that are flip-chip bonded onto a silicon CMOS integrated circuit. In the assembled module a polarization-selective computer-generated hologram converts linearly polarized light into a two-dimensional spot array to illuminate the output modulators. The lenslets do not interfere with the input data or the reflected output, which is orthogonally polarized. We demonstrate a 9x10 modulator array, showing good spot-intensity uniformity and registration with modulators.

Dual-function detector-modulator smart-pixel module.

We describe a smart-pixel circuit that permits the use of a GaAs/AlGaAs multiple quantum well diode to be used both as a detector for data input and a modulator for data output. The module provides the ability to double the number of inputs or outputs to the array and is well suited to cascaded optoelectronic system architectures that require bidirectional communition.

Polarization-controlled multistage switch based on polarization-selective computer-generated holograms.

We describe a polarization-controlled free-space optical multistage interconnection network based on polarization-selective computer-generated holograms: optical elements that are capable of imposing arbitrary, independent phase functions on horizontally and vertically polarized monochromatic light. We investigate the design of a novel nonblocking space-division photonic switch architecture. The multistage-switch architecture uses a fan-out stage, a single stage of 2 x 2 switching elements, and a fan-in stage. The architecture is compatible with several control strategies that use 1 x 2 and 2 x 2 polarization-controlled switches to route the input light beams. One application of the switch is in a passive optical network in which data is optically transmitted through the switch with a time-of-flight delay but without optical-to-electrical conversions at each stage. We have built and characterized a proof-of-principle 4 x 4 free-space switching network using three cascaded stages of arrayed birefringent computer-generated holographic elements. Data modulated at 20 MHz/channel were transmitted through the network to demonstrate transparent operation.

Photonic page buffer based on GaAs multiple-quantum-well modulators bonded directly over active silicon complementary-metal-oxide-semiconductor (CMOS) circuits.

We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This photonic chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance to jitter or skew, spatial format conversion, wavelength conversion, and independent flow control for the input and the output channels. It serves as an interface chip for parallel-accessed optical bit-plane data. It represents the first smart-pixel array that accomplishes the vertical integration of multiple-quantum-well modulators and detectors directly over active silicon VLSI circuits and provides over 340 transistors per optical input-output. Results from high-speed single-channel testing and real-time array operation of the photonic page buffer are reported.

Photonic page buffer based on GaAs multiple-quantum-well modulators bonded directly over active silicon complementary-metal-oxide-semiconductor (CMOS) circuits: errata.

Owing to printing errors, [Appl. Opt. 35, 2439 (1996)] several figures were illegible. The figures are reprinted and briefly reviewed.

Photonic content-addressable memory system that uses a parallel-readout optical disk.

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 × 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Motionless-head parallel readout optical-disk system.

The design, analysis, and feasibility of a novel motionless-head parallel readout optical-disk system are presented. The system is designed to read data blocks distributed radially on the disk's active surface, and it has the unique advantage that no mechanical motion of the head is required for fast access, focusing, or tracking. Data access is achieved solely through the disk rotation, and the entire memory can be read in one rotation. In principle, this permits a data rate of up to 1 Gbyte/s. The data blocks are one-dimensional Fourier-transform computer-generated holograms, each reconstructing one column of a two-dimensional output image. Owing to the information redundancy and shift invariance properties of Fourier-transform holograms, tracking and focusing servo requirements are eliminated. A holographic encoding method is developed to produce high signal-to-noise ratio reconstructions and to reduce significantly the radial alignment requirements of the recorded data bits. The optical readout system consists of only three cylindrical lenses. Two of these may be replaced by a single hybrid diffractive-refractive optical element for easier system alignment and better optical performance, i.e., reduced aberrations and improved resolution. The throughputs and retrieval times of this parallel readout optical-disk system make it well suited to a variety of parallel computing architectures, including a high-performance optoelectronic associative memory [Proc. Soc. Photo-Opt. Instrum. Eng. 1347, 86 (1990)].

A scalable optoelectronic neural system using free-space optical interconnects.

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.

Grain-size considerations for optoelectronic multistage interconnection networks.

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN's.

Dual-scale topology optoelectronic processor.

The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.