An improved strategy for transferring and adhering thin nanoporous alumina membranes onto conducting transparent electrodes for template assisted electrodeposition of high aspect ratio semiconductor nanowires with increased optical absorption.

This article presents a new method for transferring and enhancing the adhesion of thin nanoporous alumina (NPA) membranes onto non-atomically flat substrates like fluorine-doped tin oxide (FTO) coated glass. The study reports use of glycerol as an additive to reduce the brittleness of the polystyrene filler that was used to fill the pores of the NPA membrane. Additionally, a new reflux-based method is reported here for the complete removal of the polystryrene filler from the porous channels of alumina. The adhesion between an NPA membrane and an underlying electrode was enhanced by electrodepositing a thin (∼40 nm) intermediate layer of the conducting polymer polyaniline (PANI). The PANI layer acts as an efficient electrostatic adhesive between the NPA and the conducting glass electrode and ensures ultra-strong adhesion of the NPA membrane, which can survive the harsh conditions of CdTe nanowire electrodeposition (60 °C temperature and an acidic electrolyte) without delamination for 30 min. The resulting nanowires clearly templated the structure of NPA and displayed free-standing nanowires over a large area with a diameter of around 60 nm, a length of approximately 2.8 µm (aspect ratio ∼47) and an areal density of 5.9 × 1012 nanowires cm-2. Total optical absorption measurement on the free-standing CdTe nanowires exhibited a 45% enhancement over a wavelength range of 350-1400 nm as compared to a CdTe planar thin film of same thickness.

Charge Carrier Transport Mechanism Based on Stable Low Voltage Organic Bistable Memory Device.

A solution processed two terminal organic bistable memory device was fabricated utilizing films of polymethyl methacrylate PMMA/ZnO/PMMA on top of ITO coated glass. Electrical characterization of the device structure showed that the two terminal device exhibited favorable switching characteristics with an ON/OFF ratio greater than 1 x 10(4) when the voltage was swept between - 2 V and +3 V. The device maintained its state after removal of the bias voltage. The device did not show degradation after a 1-h retention test at 120 degrees C. The memory functionality was consistent even after fifty cycles of operation. The charge transport switching mechanism is discussed on the basis of carrier transport mechanism and our analysis of the data shows that the charge carrier trans- port mechanism of the device during the writing process can be explained by thermionic emission (TE) and space-charge-limited-current (SCLC) mechanism models while erasing process could be explained by the FN tunneling mechanism. This demonstration provides a class of memory devices with the potential for low-cost, low-power consumption applications, such as a digital memory cell.