Nonvolatile Memory (NVM) Operation of Tunnel Field-Effect Transistor (TFET) Using Ferroelectric HfO2 Sidewall.

In this paper, we propose a new type of nonvolatile memory (NVM) device based on a tunnel field-effect transistor (TFETs) with Ferroelectric HfO2 sidewall. By simply utilizing the ferroelectricity of orthorhombic HfO2 and conventional sidewall spacer technique, TFET can operate as a NVM device. The polarized charges in the ferroelectric HfO2 spacer induced by program/erase pulse modulate the tunneling barrier between the source and channel; thus, change the threshold voltage (Vt) of TFET. The proposed NVM TFET has lower subthreshold swing (SS) and higher on/off ratio than conventional NVM TFETs while maintaining equivalent program/erase efficiency. Further-more, we also investigate the optimal HfO2 sidewall formation conditions to achieve higher NVM performances.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS).

Self-Boosted Tunnel Field-Effect Transistor Using Nitride Charge Trapping Layer for Low Supply Voltage Operation.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations. Trapped charges in the nitride layer improve subthreshold characteristics and on-current (I(ON)) of both nTFET and pTFET during gate bias sweep. In addition, the benefits of the self-boosted TFET devices to low supply voltage system application are investigated. Energy consumption and propagation delay of both conventional and self-boosted TFET inverters are compared by the mixed-mode circuit simulation study. Energy consumption is almost same but the propagation delay of the self-boosted TFET inverter is reduced especially for ultra-low voltage operation where system delay is increased dramatically.

Clinical outcomes and considerations of the lumbar interbody fusion technique for lumbar disk disease in adolescents.

PURPOSE: The posterior lumbar interbody fusion (PLIF) and transforaminal lumbar interbody fusion (TLIF) techniques are commonly used surgical methods for wide indications such as degeneration or trauma. Although they are rarely required for lumbar disk disease in younger patients, there are a few children and adolescents who are indicated for PLIF or TLIF for other reasons, such as congenital severe stenosis with or without lumbar instability that requires wide decompression or severe bony spur that need to be removed. In such cases, different pathophysiology and outcomes are expected compared with adult patients. METHODS: We retrospectively reviewed data of 23 patients who underwent PLIF or TLIF surgery when less than 20 years old. Clinical and radiographic outcomes were assessed during a mean of 36.4 months follow-up period. The indications of lumbar interbody fusion, success of fusion, complications, and visual analog scale (VAS) were analyzed. RESULTS: Radiographs of all patients taken 6 months after the surgery showed fusion. Clinical outcome was also satisfactory, with improvement of VAS score from 7.7 preoperatively to 2.3 at 6 months after surgery. Only one patient had reoperation due to adjacent segment disease. CONCLUSIONS: For adolescent patients with severe bony spur, massive central disk rupture, or severe spondylolisthesis, lumbar interbody fusion surgery has good surgical outcome with few complications.

Split-gate-structure 1T DRAM for retention characteristic improvement.

As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.