ABSTRACT
We have studied electronic transport in undoped GaAs/SrTiO3core-shell nanowires standing on their Si substrate with two-tip scanning tunneling microscopy in ultrahigh vacuum. The resistance profile along the nanowires is proportional to the tip separation with resistances per unit length of a few GΩ/µm. Examination of the different transport pathways parallel to the nanowire growth axis reveals that the measured resistance is consistent with a conduction along the interfacial states at the GaAs{110} sidewalls, the 2 nm thick SrTiO3shell being as much as resistive, despite oxygen deficient growth conditions. The origin of the shell resistivity is discussed in light of the nanowire analysis with transmission electron microscopy and Raman spectroscopy, providing good grounds for the use of SrTiO3shells as gate insulators.
ABSTRACT
Correction for 'Transport mechanisms in a puckered graphene-on-lattice' by T. Xu et al., Nanoscale, 2018, 10, 7519-7525.
ABSTRACT
Understanding the fundamental properties of graphene when its topography is patterned by the use of a compliant substrate is essential to improve the performances of graphene sensors. Here we suspend a graphene monolayer on SiO2 nanopillar arrays to form a puckered graphene-on-lattice and investigate the strain and electrical transport at the nanoscale. Despite a nonuniform strain in the graphene-on-lattice, the resistivity is governed by thermally activated transport and not the strain. We show that the high thermal activation energy results from a low charge carrier density and a periodic change of the chemical potential induced by the interaction of the graphene monolayer with the nanopillars, making the use of graphene-on-lattice attractive to further increase the electrical response of graphene sensors.
