Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption.

With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent. Homomorphic encryption (HE) provides a promising solution by not only preserving data privacy but also enabling meaningful computations on encrypted data; while considerable efforts have been devoted to accelerating expensive homomorphic evaluation in the cloud, little attention has been paid to optimizing encryption and decryption (ENC-DEC) operations on the edge. In this paper, we propose efficient hardware architectures for CKKS-based ENC-DEC accelerators to facilitate computations on the client side. The proposed architectures are configurable to support a wide range of polynomial sizes with multiplicative depths (up to 30 levels) at a 128-bit security guarantee. We evaluate the hardware designs on the Xilinx XCU250 FPGA platform and achieve an average encryption time 23.7× faster than that of the well-known SEAL HE library. By reducing time complexity and improving the hardware utilization of cryptographic algorithms, our configurable CKKS-supported ENC-DEC hardware designs have the potential to greatly accelerate cryptographic processes on the client side in the post-quantum era.

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption.

The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders.

This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

Local Control of Supercurrent Density in Epitaxial Planar Josephson Junctions.

The critical current response to an applied out-of-plane magnetic field in a Josephson junction provides insight into the uniformity of its current distribution. In Josephson junctions with semiconducting weak links, the carrier density, and therefore the overall current distribution, can be modified electrostatically via metallic gates. Here, we show local control of the current distribution in an epitaxial Al-InAs Josephson junction equipped with five minigates. We demonstrate that not only can the junction width be electrostatically defined but also the current profile can be locally adjusted to form superconducting quantum interference devices. Our studies show enhanced edge conduction in such long junctions, which can be eliminated by minigates to create a uniform current distribution.

Note: Development of a wideband amplifier for cryogenic scanning tunneling microscopy.

A wideband cryogenic amplifier has been developed for low temperature scanning tunneling microscopy. The amplifier consisting of a wideband complementary metal oxide semiconductor field effect transistors operational amplifier together with a feedback resistor of 100 kΩ and a capacitor is mounted within a 4 K Dewar. This amplifier has a wide bandwidth and is successfully applied to scanning tunneling microscopy applications at low temperatures down to ∼7 K. The quality of the designed amplifier is validated by high resolution imaging. More importantly, the amplifier has also proved to be capable of performing scanning tunneling spectroscopy measurements, showing the detection of the Shockley surface state of the Au(111) surface and the superconducting gap of Nb(110).