Quantized Convolutional Neural Network Implementation on a Parallel-Connected Memristor Crossbar Array for Edge AI Platforms.

There are many challenges in the hardware implementation of a neural network using nanoscale memristor crossbar arrays where the use of analog cells is concerned. Multi-state or analog cells introduce more stringent noise margins, which are difficult to adhere to in light of variability. We propose a potential solution using a 1-bit memristor that stores binary values "0" or "1" with their memristive states, denoted as a high-resistance state (HRS) and a low-resistance state (LRS). In addition, we propose a new architecture consisting of 4-parallel 1-bit memristors at each crosspoint on the array. The four 1-bit memristors connected in parallel represent 5 decimal values according to the number of activated memristors. This is then mapped to a synaptic weight, which corresponds to the state of an artificial neuron in a neural network. We implement a convolutional neural network (CNN) model on a framework (tensorflow) using an equivalent quantized weight mapping model that demonstrates learning results almost identical to a high-precision CNN model. This radix-5 CNN is mapped to hardware on the proposed parallel-connected memristor crossbar array. Also, we propose a method for negative weight representation on a memristor crossbar array. Then, we verify the CNN hardware on an edge-AI (e-AI) platform, developed on a field-programmable gate array (FPGA). In this e-AI platform, we represent five weights per crosspoint using CLB logics. We test the learning results of the CNN hardware using an e-AI platform with a dataset consisting of 4×4 images in three classes. We verify the functionality of our radix-5 CNN implementation showing comparable classification accuracy to high-precision use cases, with reduction of the area of the memristor crossbar array by half, all verified on a FPGA. Implementing the CNN model on the FPGA board can contribute to the practical use of edge-AI.

A Leaky-Integrate-and-Fire Neuron Model of Spontaneous Reset of Thin-Film Metal-Oxide Resistive Switches.

Resistive switches in crossbar arrays introduce one potential option to push past the limits of CMOS process scaling, with advantages including low switching thresholds (<3 V), high integrability with CMOS, and fast switching speeds (<10 ns). These typically employ a 1T1R scheme for each cell, where the transistor is deployed for selection and sneak path mitigation. However, when conductive filaments are formed in metal-oxide resistive switches, it is often the case that analog states are not thermodynamically favorable, and will spontaneously set or reset to a more stable state. This causes stochastic switching, variability, and non-reproducibility, in a manner which cannot be harnessed in stochastic gradient descent. Equally important is the memory leakage problem that is introduced. In this work, we present a generalized neuron model of resistive switching in the development of a phase plane characterization, and verify its operation by comparing it to our own in-house fabricated thin-film titanium-oxide memristor array. We show an alternative design methodology that draws inspiration from the leaky-integrate-and-fire neuron model. The advantages exhibited by such a methodology are to provide more biologically accurate neuronal model and to enable large scale simulations, demonstrated by the 30% improvement in speed over similar device models.

Nano-Programmable Logics Based on Double-Layer Anti-Facing Memristors.

The memristor, as theorized by Chua in 1971 (L. Chua, IEEE Trans. Circuit Theory 18, 507 (1971)), is a two-terminal device whose resistance state is based on the history of charge flow brought about as a result of the voltage applied across its terminals. High-density regular fabrics for nanoscale memristors, such as crossbar arrays, are emerging architectures for system-on-chip (SoC) implementation, which provide both simplified structure and improved performance (W. H. Yu, et al., IEEE Trans. VLSI 20, 1012 (2012)). The advantage of using memristors as the switching devices within crossbar arrays is their nanoscale switching capability, which specifically changes their resistance state between high and low. In this paper, we propose a new nano-programmable logic array (PLA) device in the form of an on anti-facing double-layer memristor array. The PLA is composed of an AND plane and an OR plane merged onto the same layer. The AND and OR planes are stacked vertically such that each layer forms a crossbar architecture; thus, a cross section reveals two anti-facing memristors with 5 layers: the bottom metal layer, a memristive layer, the intermediate metal layer, an anti-facing memristive layer, and the top metal layer. The intermediate metal layer provides its output at the AND plane which is the input of the OR plane, and as such, the input and output nodes of the two logic functions are shared. Thus, the proposed architecture reduces the propagation delay of the AND plane by 70% by sharing the OR plane input wires. Additionally, the anti-facing architecture makes it easy to determine appropriate values for the pull-up and pull-down registers of the PLA.