Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors.

The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications.

Formation of Cluster-Structured Metallic Filaments in Organic Memristors for Wearable Neuromorphic Systems with Bio-Mimetic Synaptic Weight Distributions.

With increasing demand for wearable electronics capable of computing huge data, flexible neuromorphic systems mimicking brain functions have been receiving much attention. Despite considerable efforts in developing practical neural networks utilizing several types of flexible artificial synapses, it is still challenging to develop wearable systems for complex computations due to the difficulties in emulating continuous memory states in a synaptic component. In this study, polymer conductivity is analyzed as a crucial factor in determining the growth dynamics of metallic filaments in organic memristors. Moreover, flexible memristors with bio-mimetic synaptic functions such as linearly tunable weights are demonstrated by engineering the polymer conductivity. In the organic memristor, the cluster-structured filaments are grown within the polymer medium in response to electric stimuli, resulting in gradual resistive switching and stable synaptic plasticity. Additionally, the device exhibits the continuous and numerous non-volatile memory states due to its low leakage current. Furthermore, complex hardware neural networks including ternary logic operators and a noisy image recognitions system are successfully implemented utilizing the developed memristor arrays. This promising concept of creating flexible neural networks with bio-mimetic weight distributions will contribute to the development of a new computing architecture for energy-efficient wearable smart electronics.

Definition of a Localized Conducting Path via Suppressed Charge Injection in Oxide Memristors for Stable Practical Hardware Neural Networks.

Oxide-based memristors have been demonstrated as suitable options for memory components in neuromorphic systems. In such devices, the resistive switching characteristics are caused by the formation of conductive filaments (CFs) comprising oxygen vacancies. Thus, the electrical performance is primarily governed by the CF structure. Despite various approaches for regulating the oxygen vacancy distributions in oxide memristors, controlling the CF structure without modifying the device configuration related to material compatibility is still a challenge. This study demonstrates an effective strategy for localizing CF distributions in memristors by suppressing charge injection during the formation of conducting paths. As the injected charge quantity is reduced in the electroforming process of the oxide memristor, the CF distributions become narrower, leading to more reproducible and stable resistive switching characteristics in the device. Based on these findings, a reliable hardware neural network comprising oxide memristors is constructed to recognize complex images. The developed memristor has been employed as a synaptic memory component in systems without degradation for a long time. This promising concept of oxide memristors acting as stable synaptic components holds great potential for developing practical neuromorphic systems and their expansion into artificial intelligent systems.

Sol-Gel-Processed Y2O3 Multilevel Resistive Random-Access Memory Cells for Neural Networks.

Yttrium oxide (Y2O3) resistive random-access memory (RRAM) devices were fabricated using the sol-gel process on indium tin oxide/glass substrates. These devices exhibited conventional bipolar RRAM characteristics without requiring a high-voltage forming process. The effect of current compliance on the Y2O3 RRAM devices was investigated, and the results revealed that the resistance values gradually decreased with increasing set current compliance values. By regulating these values, the formation of pure Ag conductive filament could be restricted. The dominant oxygen ion diffusion and migration within Y2O3 leads to the formation of oxygen vacancies and Ag metal-mixed conductive filaments between the two electrodes. The filament composition changes from pure Ag metal to Ag metal mixed with oxygen vacancies, which is crucial for realizing multilevel cell (MLC) switching. Consequently, intermediate resistance values were obtained, which were suitable for MLC switching. The fabricated Y2O3 RRAM devices could function as a MLC with a capacity of two bits in one cell, utilizing three low-resistance states and one common high-resistance state. The potential of the Y2O3 RRAM devices for neural networks was further explored through numerical simulations. Hardware neural networks based on the Y2O3 RRAM devices demonstrated effective digit image classification with a high accuracy rate of approximately 88%, comparable to the ideal software-based classification (~92%). This indicates that the proposed RRAM can be utilized as a memory component in practical neuromorphic systems.

Low-Temperature Enhancement-Mode Amorphous Oxide Thin-Film Transistors in Solution Process Using a Low-Pressure Annealing.

The interest in low processing temperature for printable transistors is rapidly increasing with the introduction of a new form factor in electronics and the growing importance of high throughput. This paper reports the fabrication of low-temperature-processable enhancement-mode amorphous oxide thin-film transistors (TFTs) using the solution process. A facile low-pressure annealing (LPA) method is proposed for the activation of indium oxide (InOx) semiconductors at a significantly low processing temperature of 200 °C. Thermal annealing at a pressure of about ~10 Torr induces effective condensation in InOx even at a low temperature. As a result, the fabricated LPA InOx TFTs not only functioned in enhancement mode but also exhibited outstanding switching characteristics with a high on/off current ratio of 4.91 × 109. Furthermore, the LPA InOx TFTs exhibit stable operation under bias stress compared to the control device due to the low concentration of hydroxyl defects.

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley-Read-Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

One-Stop Strategy for Obtaining Controllable Sensitivity and Feasible Self-Patterning in Silver Nanowires/Elastomer Nanocomposite-Based Stretchable Ultrathin Strain Sensors.

In this study, selective photo-oxidation (SPO) is proposed as a simple, fast, and scalable one-stop strategy that enables simultaneous self-patterning and sensitivity adjustment of ultrathin stretchable strain sensors. The SPO of an elastic substrate through irradiation time-controlled ultraviolet treatment in a confined region enables precise tuning of both the surface energy and the elastic modulus. SPO induces the hydrophilization of the substrate, thereby allowing the self-patterning of silver nanowires (AgNWs). In addition, it promotes the formation of nonpermanent microcracks of AgNWs/elastomer nanocomposites under the action of strain by increasing the elastic modulus. This effect improves sensor sensitivity by suppressing the charge transport pathway. Consequently, AgNWs are directly patterned with a width of 100 µm or less on the elastic substrate, and AgNWs/elastomer-based ultrathin and stretchable strain sensors with controlled sensitivity work reliably in various operating frequencies and cyclic stretching. Sensitivity-controlled strain sensors successfully detect both small and large movements of the human hand.

Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc-Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment.

In this study, we used a low-pressure thermal annealing (LPTA) treatment to improve the switching characteristics and bias stability of zinc-tin oxide (ZTO) thin film transistors (TFTs). For this, we first fabricated the TFT and then applied the LPTA treatment at temperatures of 80 °C and 140 °C. The LPTA treatment reduced the number of defects in the bulk and interface of the ZTO TFTs. In addition, the changes in the water contact angle on the ZTO TFT surface indicated that the LPTA treatment reduced the surface defects. Hydrophobicity suppressed the off-current and instability under negative bias stress because of the limited absorption of moisture on the oxide surface. Moreover, the ratio of metal-oxygen bonds increased, while the ratio of oxygen-hydrogen bonds decreased. The reduced action of hydrogen as a shallow donor induced improvements in the on/off ratio (from 5.5 × 103 to 1.1 × 107) and subthreshold swing (8.63 to V·dec-1 and 0.73 V·dec-1), producing ZTO TFTs with excellent switching characteristics. In addition, device-to-device uniformity was significantly improved because of the reduced defects in the LPTA-treated ZTO TFTs.

Organic Memristor-Based Flexible Neural Networks with Bio-Realistic Synaptic Plasticity for Complex Combinatorial Optimization.

Hardware neural networks with mechanical flexibility are promising next-generation computing systems for smart wearable electronics. Several studies have been conducted on flexible neural networks for practical applications; however, developing systems with complete synaptic plasticity for combinatorial optimization remains challenging. In this study, the metal-ion injection density is explored as a diffusive parameter of the conductive filament in organic memristors. Additionally, a flexible artificial synapse with bio-realistic synaptic plasticity is developed using organic memristors that have systematically engineered metal-ion injections, for the first time. In the proposed artificial synapse, short-term plasticity (STP), long-term plasticity, and homeostatic plasticity are independently achieved and are analogous to their biological counterparts. The time windows of the STP and homeostatic plasticity are controlled by the ion-injection density and electric-signal conditions, respectively. Moreover, stable capabilities for complex combinatorial optimization in the developed synapse arrays are demonstrated under spike-dependent operations. This effective concept for realizing flexible neuromorphic systems for complex combinatorial optimization is an essential building block for achieving a new paradigm of wearable smart electronics associated with artificial intelligent systems.

Improved Environment Stability of Y2O3 RRAM Devices with Au Passivated Ag Top Electrodes.

In this study, we fabricated sol-gel-processed Y2O3-based resistive random-access memory (RRAM) devices. The fabricated Y2O3 RRAM devices exhibited conventional bipolar RRAM device characteristics and did not require the forming process. The long-term stability of the RRAM devices was investigated. The Y2O3 RRAM devices with a 20 nm thick Ag top electrode showed an increase in the low resistance state (LRS) and high resistance state (HRS) and a decrease in the HRS/LRS ratio after 30 days owing to oxidation and corrosion of the Ag electrodes. However, Y2O3 RRAM devices with inert Au-passivated Ag electrodes showed a constant RRAM device performance after 30 days. The 150 nm-thick Au passivation layer successfully suppressed the oxidation and corrosion of the Ag electrode by minimizing the chance of contact between water or oxygen molecules and Ag electrodes. The Au/Ag/Y2O3/ITO RRAM devices exhibited more than 300 switching cycles with a decent resistive window (>103). They maintained constant LRS and HRS resistances for up to 104 s, without significant degradation of nonvolatile memory properties for 30 days while stored in air.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 µA/µm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Organizing Reliable Polymer Electrode Lines in Flexible Neural Networks via Coffee Ring-Free Micromolding in Capillaries.

With an increase in the demand for smart wearable systems, artificial synapse arrays for flexible neural networks have received considerable attention. A synaptic device with a two-terminal configuration is promising for complex neural networks because of its ability to scale to a crossbar array architecture. To realize practical crossbar arrays with a high density, it is essential to achieve reliable electrode lines that act as signal terminals. However, an effective method to develop intrinsically flexible signal lines in artificial neural networks has not been developed. In this study, we achieved reliable polymer signal lines for flexible neural networks using coffee ring-free micromolding in capillaries (MIMIC). In a typical MIMIC, the outward convective flow of the polymer solution inherently deteriorates the pattern fidelity. To achieve reliable conducting polymer (CP) lines, we precisely controlled the flow of the polymer solution in the MIMIC by inducing the Marangoni force. When the convective and Marangoni flows for the solution were balanced in the MIMIC, the CP line patterns were reliably produced with high fidelity. The developed CP lines exhibited superior conductivity and high mechanical flexibility. Moreover, flexible memristor arrays consisting of CP signal lines demonstrated a high potential for realizing practical neuromorphic systems linked to artificial intelligence.

Importance of Structural Relaxation on the Electrical Characteristics and Bias Stability of Solution-Processed ZnSnO Thin-Film Transistors.

Effect of structural relaxation (SR) on the electrical characteristics and bias stability of solution-processed zinc-tin oxide (ZTO) thin-film transistors (TFTs) were systematically investigated by controlling the annealing time of the ZTO semiconductor films. Note that SR was found to increase with increased annealing time. Due to the increased SR, the ratio of oxygen vacancies (VO) increased from 21.5% to 38.2%. According to increased VO, the mobility in the saturation region was exhibited by a sixfold increase from 0.38 to 2.41 cm2 V-1 s-1. In addition, we found that the threshold voltage negatively shifted from 3.08 to -0.95 V. Regarding the issue of bias stability, according to increased SR, positive-bias stress of the ZTO TFTs was enhanced, compared with reverse features of negative-bias stress. Our understanding is expected to provide a basic way to improve the electrical characteristics and bias stability of rare-metal-free oxide semiconductor TFTs, which have not been sufficiently studied.

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary's influence.

In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

Room-Temperature High-Detectivity Flexible Near-Infrared Photodetectors with Chalcogenide Silver Telluride Nanoparticles.

Herein, flexible near-infrared (NIR) photodetectors were prepared using silver telluride (Ag5Te3) nanoparticles (NPs) for optoelectronic applications. For the main channel materials of the photodetectors, Ag5Te3 NPs were used, which were synthesized in an aqueous solution. Moreover, Ag5Te3 thin films were successfully fabricated on plastic substrates at 150 °C using redistributed Ag5Te3 NPs in aqueous inks. The crystal structure, chemistry, and optoelectronic properties of the synthesized photodetectors were studied. The fabricated flexible Ag5Te3-based photodetectors achieved a detectivity of 6.27 × 109 cm Hz1/2 W-1 (>109) at room temperature under ∼0.35% compressive and tensile strains. The obtained detectivity value exceeds those of two-dimensional inorganic layered material phototransistors-such as MoS2-or commercial thermistor bolometers at room temperature (∼109). Furthermore, the proposed novel method for the synthesis of Ag5Te3 thin films on plastic substrates can be applied to other Ag5Te3-based applications in the future.

Flexible Sol-Gel-Processed Y2O3 RRAM Devices Obtained via UV/Ozone-Assisted Photochemical Annealing Process.

Flexible indium tin oxide (ITO)/Y2O3/Ag resistive random access memory (RRAM) devices were successfully fabricated using a thermal-energy-free ultraviolet (UV)/ozone-assisted photochemical annealing process. Using the UV/ozone-assisted photochemical process, the organic residue can be eliminated, and thinner and smother Y2O3 films than those formed using other methods can be fabricated. The flexible UV/ozone-assisted photochemical annealing process-based ITO/Y2O3/Ag RRAM devices exhibited the properties of conventional bipolar RRAM without any forming process. Furthermore, the pure and amorphous-phase Y2O3 films formed via this process showed a decreased leakage current and an increased high-resistance status (HRS) compared with the films formed using other methods. Therefore, RRAM devices can be realized on plastic substrates using a thermal-energy-free UV/ozone-assisted photochemical annealing process. The fabricated devices exhibited a resistive window (ratio of HRS/low-resistance status (LRS)) of >104, with the HRS and LRS values remaining almost the same (i.e., limited deterioration occurred) for 104 s and up to 102 programming/erasing operation cycles.

Enhanced Switching Reliability of Sol-Gel-Processed Y2O3 RRAM Devices Based on Y2O3 Surface Roughness-Induced Local Electric Field.

Sol-gel-processed Y2O3 films were used as active channel layers for resistive random access memory (RRAM) devices. The fabricated ITO/Y2O3/Ag RRAM devices exhibited the properties of conventional bipolar memory devices. A triethylamine stabilizer with a high vapor pressure and low surface tension was added to realize the local electric field area. During drying and high-temperature post-annealing processes, the large convective flow enhanced the surface elevation, and the increased -OH groups accelerated the hydrolysis reaction and aggregation. These phenomena afforded Y2O3 films with an uneven surface morphology and an increased surface roughness. The increased roughness of the Y2O3 films attributable to the triethylamine stabilizer enhanced the local electrical field, improved device reliability, and achieved successful repetition of the switching properties over an extended period.

Environmentally and Electrically Stable Sol-Gel-Deposited SnO2 Thin-Film Transistors with Controlled Passivation Layer Diffusion Penetration Depth That Minimizes Mobility Degradation.

This study examines the effect of the annealing time of the Y2O3 passivation layer on the electrical performances and bias stabilities of sol-gel-deposited SnO2 thin-film transistors (TFTs). The environmental stabilities of SnO2 TFTs were examined. After optimizing the Y2O3 passivation layers in SnO2 TFTs, the field-effect mobility was 7.59 cm2/V•s, the VTH was 9.16 V, the subthreshold swing (SS) was 0.88 V/decade, and the on/off-current ratio was approximately 1 × 108. VTH shifts were only -0.18 and +0.06 V under negative and positive bias stresses, respectively. The SnO2 channel layer thickness and oxygen-vacancy concentration in SnO2, which determine the carrier concentration, were successfully tuned by controlling the annealing time of the Y2O3 passivation layers. An extremely thin Y2O3 passivation layer effectively blocked external molecules, thus affecting the device performance. The electrical performance was maximized in SnO2 TFTs using a 15 min-annealed Y2O3 passivation layer. In this TFT, the field-effect mobility was maximally retained and the bias and environmental stabilities were sustained over 90 days of air exposure.

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator.

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO2/Si3N4 dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si3N4 single-layer insulator are conducted to the simulation works together. The stacked TiO2/Si3N4 GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO2/Si3N4 than that of a Si3N4 single-layer insulator. However, the electrical field and current density increased by the stacked TiO2/Si3N4 layers make the device's temperature higher. That results in the degradation of the device's performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO2/Si3N4-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; Ron increased from 1.41 mΩ·cm2 to 2.56 mΩ·cm2, and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO2/Si3N4-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si3N4 single-layer insulator.

Enhancement of Charge Injection in Organic Field-Effect Transistors Through Semiconducting Organic Buffer Layer.

We investigate the effect of a semiconducting organic buffer layer (SOBL) on the injection and transport of charges in organic field-effect transistors (OFETs). Here, two different injection barriers at the source/organic semiconductor interface are respectively studied with the aid of a numerical simulation: one is intermediate (0.4 eV), and the other is large energy barriers (0.6 eV). The introduction of nanostructure buffer layer, or SOBL, exhibits the decrease of potential loss at the contact interfaces, improving the electrical performance of the OFETs. It is also found that the energy level as well as the mobility of the SOBL plays an important role in determining the injection properties at the metal/organic hetero-interfaces and thus improving the device performance. Our systematic investigation on the injection barrier by the introduction of the nanostructure buffer layer will provide a useful guideline for the fabrication of high-performance FETs with molecular semiconductors.