Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications.

The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed.

Field programmable gate arrays implementation of Dual Tree Complex Wavelet Transform.

Due to the inherent time-varying characteristics of physiological systems, most biomedical signals (BSs) are expected to have non-stationary character. Therefore, any appropriate analysis method for dealing with BSs should exhibit adjustable time-frequency (TF) resolution. The wavelet transform (WT) provides a TF representation of signals, which has good frequency resolution at low frequencies and good time resolution at high frequencies, resulting in an optimized TF resolution. Discrete wavelet transform (DWT), which is used in various medical signal processing applications such as denoising and feature extraction, is a fast and discretized algorithm for classical WT. However, the DWT has some very important drawbacks such as aliasing, lack of directionality, and shift-variance. To overcome these drawbacks, a new improved discrete transform named as Dual Tree Complex Wavelet Transform (DTCWT) can be used. Nowadays, with the improvements in embedded system technology, portable real-time medical devices are frequently used for rapid diagnosis in patients. In this study, in order to implement DTCWT algorithm in FPGAs, which can be used as real-time feature extraction or denoising operator for biomedical signals, a novel hardware architecture is proposed. In proposed architecture, DTCWT is implemented with only one adder and one multiplier. Additionally, considering the multi-channel outputs of biomedical data acquisition systems, this architecture is capable of running N channels in parallel.