Doping-Less Feedback Field-Effect Transistors.

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, DLFBFETs are virtually doped through charge plasma phenomena caused by the source, the drain, and the dual-gate electrodes as well as the gate biases. Our DLFBFETs can be fabricated through a simple process of creating contact between a metal and a silicon body without any doping processes. The voltages applied to both gates determine whether the DLFBFETs operate in diode or feedback field-effect transistor (FBFET) modes. In the FBFET mode, our DLFBFETs show good characteristics such as an on/off current ratio of ~104 and steep switching characteristics (~1 mV/decade of current) that result from positive feedback phenomena without dopants.

Reconfigurable Feedback Field-Effect Transistors with a Single Gate.

In this study, we present a reconfigurable feedback field-effect transistor (FET) that can operate in both p- and n-type configurations using a feedback mechanism. In contrast to previously reported reconfigurable FETs, our device utilizes a single gate to trigger a feedback mechanism at the center, resulting in steep switching characteristics. The device exhibited high symmetry of transfer characteristics, an on/off current ratio of approximately 1010, extremely low subthreshold swings, and a high on-current of approximately 1.5 mA at low gate voltages in both configurations. In addition, because of their hysteresis and bistable characteristics, they can be applied to various electronic devices. These characteristics were analyzed using a commercial device simulator.

Temperature-Dependent Electrical Characteristics of Silicon Biristor.

In this study, we investigate the temperature-dependent electrical characteristics of bistable silicon resistors (biristors) at temperatures ranging from 275 to 400 K. The proposed biristor exhibits low latch voltages owing to the surface accumulation layer transistor concept. Moreover, the biristor was abruptly turned on and off by positive and negative feedback phenomena, respectively. As the temperature increased from 275 to 400 K, the latch-up voltage decreased from 2.131 to 1.696 V, while the latch-down voltage increased from 1.486 to 1.637 V. Mechanisms of temperature-dependent change in latch voltage were analyzed using energy band diagrams. This temperature-dependent analysis on silicon biristor can serve as blueprint for the contribution of stable operation.

Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping.

In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p+-i-n+silicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel. The SiNW RFET features simple device design, symmetrical electrical characteristics in the n- and p-channel operation modes using p+-i-n+diode characteristics, and both operation modes exhibit high ON/OFF ratios (∼106) and high ON currents (∼1µAµm-1). The proposed device is demonstrated experimentally using a fully CMOS-compatible top-down processes.

Integrate-and-Fire Neuron Circuit Without External Bias Voltages.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

Effect of Ge Mole Fraction on Performance of Underlapped Gate-All-Around SiGe-Source Tunneling Field-Effect Transistors.

In this paper, we propose the design optimization of underlapped Si1-xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I-V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1-xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

Steep Switching Characteristics of Partially Gated p+-n+-i-n+ Silicon-Nanowire Transistors.

In this study, we examine the electrical characteristics of p+-n+-i-n+ silicon-nanowire field-effect transistors with partially gated channels. The silicon-nanowire field-effect transistors operate with barrier height modulation through positive feedback loops of charge carriers triggered by impact ionization. Our field-effect transistors exhibit outstanding switching characteristics, with an on current of ˜10-4 A, an on/off current ratio of ˜106, and a point subthreshold swing of ˜23 mV/dec. Moreover, the devices inhibit ambipolar characteristics because of the use of the partially gated structure and feature the p-channel operation mode.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

Feedback and tunneling operations of a p +-i-n + silicon nanowire field-effect transistor.

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with a p +-i-n + doped silicon nanowire channel. The transistor functions selectively in either a feedback FET (FBFET) or a tunneling FET mode by modulating the source-to-drain voltage, and it features an outstanding subthreshold swing characteristic of 6.15 mV dec-1 with an on/off current ratio (I on/I off) of approximately 106 in the feedback operating mode and of 41.3 mV dec-1 with I on/I off of ∼107 in the tunneling operating mode. Moreover, our device in the FBFET operation mode has memory characteristics with a retention time of 104 s and a program/erase endurance up to 103 cycles owing to the positive feedback loop in the channel region. This study demonstrates the promising potential of our devices in the development of multifunctional electronics.

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

Memory characteristics of silicon nanowire transistors generated by weak impact ionization.

In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

Steep switching characteristics of single-gated feedback field-effect transistors.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec-1, an on/off current ratio of approximately 1011, and an on-current of approximately 10-4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p(+)-i-n(+) Nanowires by Dual-Top-Gate Voltage Modulation.

In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting of p(+)-i-n(+) Si nanowires (NWs) and dual-top-gate structures. As a result of a positive feedback loop in the intrinsic channel region, our FBFET features the outstanding switching characteristics of an on/off current ratio of approximately 10(6), and point subthreshold swings (SSs) of 18-19 mV/dec in the n-channel operation mode and of 10-23 mV/dec in the p-channel operation mode. Not only can these devices operate in n- or p-channel modes, their switching characteristics can also be modulated by adjusting the gate biases. Moreover, the device maintains its steep SS characteristics, even when the substrate is bent. This study demonstrates the promising potential of bendable NW FBFETs for use as low-power components in integrated circuits or memory devices.