High-performance GeSi/Ge multi-quantum well photodetector on a Ge-buffered Si substrate.

This work demonstrates a high-performance photodetector with a 4-cycle Ge0.86Si0.14/Ge multi-quantum well (MQW) structure grown by reduced pressure chemical vapor deposition techniques on a Ge-buffered Si (100) substrate. At -1 V bias, the dark current density of the fabricated PIN mesa devices is as low as 3 mA/cm2, and the optical responsivities are 0.51 and 0.17 A/W at 1310 and 1550 nm, respectively, corresponding to the cutoff wavelength of 1620 nm. At the same time, the device has good high-power performance and continuous repeatable light response. On the other hand, the temperature coefficient of resistance (TCR) of the device is as high as -5.18%/K, surpassing all commercial thermal detectors. These results indicate that the CMOS-compatible and low-cost Ge0.86Si0.14/Ge multilayer structure is promising for short-wave infrared and uncooled infrared imaging.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Dosimetry of intensity-modulated radiation therapy and volumetric-modulated arc therapy techniques after modified radical mastectomy for breast cancer and hypofractionated intensity-modulated radiotherapy.

OBJECTIVE: The aim of this study was to compare the advantages and disadvantages of intensity-modulated radiation therapy (IMRT) and volumetric-modulated arc therapy (VMAT) in patients with left-sided breast cancer who underwent hypofractionated IMRT after a modified radical mastectomy. MATERIALS AND METHODS: Twenty patients who required adjuvant radiotherapy after modified radical mastectomy were randomly selected, and a specified dose of 43.5 Gy/15 F was used to plan for IMRT or VMAT. Dose-volume histograms (DVHs) were utilized to evaluate the dose distribution of the planning target volumes (PTVs) and organs at risk (OARs). RESULTS: VMAT demonstrated a greater and more uniform dose distribution of PTVs and lower number of monitor units. No significant differences were found in V5 of the affected lung and heart between the two techniques (P > 0.05). The V10, V20, V30, and Dmean of the affected lung and V10, V20, V30, V40, Dmean, and Dmax of the whole heart were better in the VMAT than in the IMRT (P < 0.05). The Dmean and Dmax of the left anterior descending (LAD) branch of the coronary artery of the heart were better in the VMAT (P < 0.05), and the use of the VMAT effectively reduced the cardiopulmonary dose. A significant advantage of V30 and Dmean was also found in VMAT (P < 0.05). CONCLUSION: These findings indicate that VMAT has higher clinical significance than IMRT, because it improved the dose distribution in the target area, reduced the cardiopulmonary dose, protected the OARs (e.g. thyroid), and shortened the treatment duration.

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions.

SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiH2Cl2, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated. The interface quality was characterized by transmission electron microscopy/atomic force microscopy/high-resolution X-ray diffraction methods. It was observed that limiting the migration of Ge atoms in the interface was critical for optimizing a sharp interface, and the addition of DCS was found to decrease the interface transition thickness. The change of the interfacial transition layer is not significant in the short treatment time of HCl. When the processing time of HCl is increased, the internal interface is optimized to a certain extent but the corresponding film thickness is also reduced. This study provides technical support for the acquisition of an abrupt interface and will have a very favorable influence on the performance improvement of miniaturized devices in the future.

Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process.

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region.

Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, which will boost LiDAR applications. Although Si APDs have already been commercialized, their spectral region is very limited in many applications. Therefore, it is urgently demanded that the spectral region APDs be extended to the short-wavelength infrared (SWIR) region, which means better atmospheric transmission, a lower solar radiation background, a higher laser eye safety threshold, etc. Up until now, both Ge (GeSn) and InGaAs were employed as the SWIR absorbers. The aim of this review article is to provide a full understanding of Ge(GeSn) and InGaAs for PDs, with a focus on APD operation in the SWIR spectral region, which can be integrated onto the Si platform and is potentially compatible with CMOS technology.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm-2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 µm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-µm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III-V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.

Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer. No patterned substrate or sophisticated superlattice defect-filtering layer was involved. Thanks to the improved quality of the comprehensively modified GaAs crystal with low defect density, the room temperature emission wavelength of this laser was allocated at 1320 nm, with a threshold current density of 24.4 A/cm-2 per layer and a maximum single-facet output power reaching 153 mW at 10 °C. The maximum operation temperature reaches 80 °C. This work provides a feasible and promising proposal for the integration of an efficient O-band laser with a standard Si platform in the near future.

Frailty's Prevalence and the Association with Aging-Related Health Conditions in Chinese Community Dwelling Elderly.

In this paper, we have investigated the frailty's prevalence and the association with aging-related health conditions in Chinese community dwelling elderly aged ≥60 years in Lianyungang City of China. In this regard, participants were 1,072 adults aged ≥60 years from Houhe Community of Lianyungang City of China. All the enrolled participants were tested for following parameters: (1) the related risk factors of frailty: including economic status, personal health, understanding and communication skills, and mental and psychological status; (2) aging-related health conditions related to frailty: Charlson's comorbidity index (CCI), Mini Nutritional Assessment Short Form (MNA-SF), Patient Health Questionnaire-9 (PHQ-9), and Generalized Anxiety Disorder 7-item (GAD-7); (3) body composition, physical strength, and function testing: appendicular skeletal muscle mass index (ASMI), grip strength, five-repetition sit-to-stand test, 6 m walking speed, and strength assistance rise-climb-fall (SARC-F); (4) assessment of the degree and severity of frailty: physical frailty phenotype (PFP), Morse fall scale (MFS), and activities of daily living (ADL). The frailty's prevalence among the elderly aged ≥60 years in the community of Lianyungang City was 13.8%, 55.4% were prefrail, and 30.8% were robust. The independent risk factors of frailty were age, appendicular skeletal muscle mass index, sarcopenia, education, nutrition, and strength assistance rise-climb-fall (P < 0.05). Aging-related health conditions were associated with frailty, including sarcopenia, nutrition, and falls. However, mental and psychological statuses were not significantly associated with frailty.

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm-2 in a globally grown Ge layer to 3.2 × 105 cm-2 for a single-step SEG and to 2.84 × 105 cm-2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications.

GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285-320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm-2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was -0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm-2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids.

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon-germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski-Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it's threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm-2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

High Performance p-i-n Photodetectors on Ge-on-Insulator Platform.

In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 µm, the dark current at -1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at -1 V are as low as 1.79 mA/cm2 and 0.34 µA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.

Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon-Germanium Multilayers Structures for Vertical Transistors Application.

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

State of the Art and Future Perspectives in Advanced CMOS Technology.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.