Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power.

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

Enhancement noise margin and delay time performance of novel punch-through nMOS for single-carrier CMOS.

In this paper, we propose the use of punch-through nMOS (PTnMOS) as an alternative to pMOS in complementary metal oxide semiconductor (CMOS) circuits. According to the TCAD simulation results, PTnMOS exhibit sub-threshold characteristics similar to those of pMOS and can be formed by simply changing the doping concentration of the source and drain. Without the need for sizing, which solves the area occupation problem caused by the need to increase the width of pMOS due to insufficient hole mobility. In addition, we compose a PTnMOS and nMOS without sizing to form a single-carrier CMOS in which only electrons are transmitted, and We extract its performance for comparison with conventional CMOS (Wp/Wn = 1). The results indicate that single-carrier CMOS has symmetric noise margin and 29% faster delay time compared to conventional CMOS (Wp/Wn = 1). If III-V or II-VI group materials could be applied to single-carrier CMOS, not only could costs be reduced and wafer area occupancy minimized, but also significant improvements in the performance and bandwidth application of microwave circuits could be achieved.

Investigation of SiGe/Si heterojunction inductive line tunneling TFET with source Schottky contact for prospect ultra-low power applications.

In this paper, a SiGe/Si heterojunction inductive line tunneling tunnel field-effect transistor with source Schottky contact (SC HJLT-iTFET) is proposed and investigated by the Sentaurus Technology Computer Aided Design (TCAD) simulator. By utilizing an appropriate source Schottky metal, the need for multiple ion implantation and annealing steps required for traditional P-I-N TFETs can be avoided, and the problems of self-alignment and random dopant fluctuations (RDF) during ion implantation can be solved. A high ON-state current (ION) is obtained as fully overlapping the source and gate by line tunneling mechanism dominated, the appropriate Si1-xGexmole fraction material in the source region and high-k gate dielectric employed can further improveION. The incorporation of the block layer effectively decreases the lateral electric field at the drain end to reduce the OFF-state current (IOFF). Furthermore, the proposed charge enhancement layer (CEL) on the SiGe channel can suppress the Fermi level pinning effect (FLP) and enhance the charge of the source region. Based on the feasibility of the practical fabrication process, and the rigorous simulations indicate that the device has an SSavgof 19.8 mV/dec and SSminof 6.8 mV/dec atVD= 0.2 V,IONof 2.27 × 10-6Aµm-1, and anION/IOFFratio of 1.02 × 1010, with extremely fast switching speed. These features make the device suitable for future ultra-low power applications on the internet of things, artificial intelligence, and related fields.

Bilateral sidewall engineering Si1-xGexiTFET for low power display application.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve theION, resulting in a lower subthreshold swing average (S.Savg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that theS.Savgis improved to 21.5 mV dec-1with anION/IOFFratio of 106 atVD= 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec-1has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket.

In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 [Formula: see text] 10-6 A/µm, and the ION/IOFF ratio is 1.34 [Formula: see text] 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation.

In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at VD = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SSavg) of 30.5 mV/dec, an Ion of 3.12 × 10-5 A/µm and an Ion/Ioff ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement.

This article presents a new line tunneling dominating metal-semiconductor contact-induced SiGe-Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate's ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal-semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.