Improvement Performance of p-GaN Gate High-Electron-Mobility Transistors with GaN/AlN/AlGaN Barrier Structure.

This study demonstrates a particular composited barrier structure of high-electron-mobility transistors (HEMTs) with an enhancement mode composed of p-GaN/GaN/AlN/AlGaN/GaN. The purpose of the composite barrier structure device is to increase the maximum drain current, reduce gate leakage, and achieve lower on-resistance (Ron) performance. A comparison was made between the conventional device without the composited barrier and the device with the composited barrier structure. The maximum drain current is significantly increased by 37%, and Ron is significantly reduced by 23%, highlighting the synergistic impact of the composite barrier structure on device performance improvement. This reason can be attributed to the undoped GaN (u-GaN) barrier layer beneath p-GaN, which was introduced to mitigate Mg diffusion in the capping layer, thus addressing its negative effects. Furthermore, the AlN barrier layer exhibits enhanced electrical properties, which can be attributed to the critical role of high-energy-gap properties that increase the 2DEG carrier density and block leakage pathways. These traps impact the device behavior mechanism, and the simulation for a more in-depth analysis of how the composited barrier structure brings improvement is introduced using Synopsys Sentaurus TCAD.

Vertical GaN MOSFET Power Devices.

Gallium nitride (GaN) possesses remarkable characteristics such as a wide bandgap, high critical electric field, robust antiradiation properties, and a high saturation velocity for high-power devices. These attributes position GaN as a pivotal material for the development of power devices. Among the various GaN-based devices, vertical GaN MOSFETs stand out for their numerous advantages over their silicon MOSFET counterparts. These advantages encompass high-power device applications. This review provides a concise overview of their significance and explores their distinctive architectures. Additionally, it delves into the advantages of vertical GaN MOSFETs and highlights their recent advancements. In conclusion, the review addresses methods to enhance the breakdown voltage of vertical GaN devices. This comprehensive perspective underscores the pivotal role of vertical GaN MOSFETs in the realm of power electronics and their continual progress.

Improving Performance and Breakdown Voltage in Normally-Off GaN Recessed Gate MIS-HEMTs Using Atomic Layer Etching and Gate Field Plate for High-Power Device Applications.

A typical method for normally-off operation, the metal-insulator-semiconductor-high electron mobility transistor (MIS-HEMT) has been investigated. Among various approaches, gate recessed MIS-HEMT have demonstrated a high gate voltage sweep and low leakage current characteristics. Despite their high performance, obtaining low-damage techniques in gate recess processing has so far proven too challenging. In this letter, we demonstrate a high current density and high breakdown down voltage of a MIS-HEMT with a recessed gate by the low damage gate recessed etching of atomic layer etching (ALE) technology. After the remaining 3.7 nm of the AlGaN recessed gate was formed, the surface roughness (Ra of 0.40 nm) was almost the same as the surface without ALE (no etching) as measured by atomic force microscopy (AFM). Furthermore, the devices demonstrate state-of-the-art characteristics with a competitive maximum drain current of 608 mA/mm at a VG of 6 V and a threshold voltage of +2.0 V. The devices also show an on/off current ratio of 109 and an off-state hard breakdown voltage of 1190 V. The low damage of ALE technology was introduced into the MIS-HEMT with the recessed gate, which effectively reduced trapping states at the interface to obtain the low on-resistance (Ron) of 6.8 Ω·mm and high breakdown voltage performance.

A Brief Overview of the Rapid Progress and Proposed Improvements in Gallium Nitride Epitaxy and Process for Third-Generation Semiconductors with Wide Bandgap.

In this paper, we will discuss the rapid progress of third-generation semiconductors with wide bandgap, with a special focus on the gallium nitride (GaN) on silicon (Si). This architecture has high mass-production potential due to its low cost, larger size, and compatibility with CMOS-fab processes. As a result, several improvements have been proposed in terms of epitaxy structure and high electron mobility transistor (HEMT) process, particularly in the enhancement mode (E-mode). IMEC has made significant strides using a 200 mm 8-inch Qromis Substrate Technology (QST®) substrate for breakdown voltage to achieve 650 V in 2020, which was further improved to 1200 V by superlattice and carbon-doped in 2022. In 2016, IMEC adopted VEECO metal-organic chemical vapor deposition (MOCVD) for GaN on Si HEMT epitaxy structure and the process by implementing a three-layer field plate to improve dynamic on-resistance (RON). In 2019, Panasonic HD-GITs plus field version was utilized to effectively improve dynamic RON. Both reliability and dynamic RON have been enhanced by these improvements.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs.

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

State-of-the-Art ß-Ga2O3 Field-Effect Transistors for Power Electronics.

Due to the emergence of electric vehicles, power electronics have become the new focal point of research. Compared to commercialized semiconductors, such as Si, GaN, and SiC, power devices based on ß-Ga2O3 are capable of handling high voltages in smaller dimensions and with higher efficiencies, because of the ultrawide bandgap (4.9 eV) and large breakdown electric field (8 MV cm-1). Furthermore, the ß-Ga2O3 bulk crystals can be synthesized by the relatively low-cost melt growth methods, making the single-crystal substrates and epitaxial layers readily accessible for fabricating high-performance power devices. In this article, we first provide a comprehensive review on the material properties, crystal growth, and deposition methods of ß-Ga2O3, and then focus on the state-of-the-art depletion mode, enhancement mode, and nanomembrane field-effect transistors (FETs) based on ß-Ga2O3 for high-power switching and high-frequency amplification applications. In the meantime, device-level approaches to cope with the two main issues of ß-Ga2O3, namely, the lack of p-type doping and the relatively low thermal conductivity, will be discussed and compared.

The Evolution of Manufacturing Technology for GaN Electronic Devices.

GaN has been widely used to develop devices for high-power and high-frequency applications owing to its higher breakdown voltage and high electron saturation velocity. The GaN HEMT radio frequency (RF) power amplifier is the first commercialized product which is fabricated using the conventional Au-based III-V device manufacturing process. In recent years, owing to the increased applications in power electronics, and expanded applications in RF and millimeter-wave (mmW) power amplifiers for 5G mobile communications, the development of high-volume production techniques derived from CMOS technology for GaN electronic devices has become highly demanded. In this article, we will review the history and principles of each unit process for conventional HEMT technology with Au-based metallization schemes, including epitaxy, ohmic contact, and Schottky metal gate technology. The evolution and status of CMOS-compatible Au-less process technology will then be described and discussed. In particular, novel process techniques such as regrown ohmic layers and metal-insulator-semiconductor (MIS) gates are illustrated. New enhancement-mode device technology based on the p-GaN gate is also reviewed. The vertical GaN device is a new direction of development for devices used in high-power applications, and we will also highlight the key features of such kind of device technology.

Advances in Quantum-Dot-Based Displays.

In terms of their use in displays, quantum dots (QDs) exhibit several advantages, including high illumination efficiency and color rendering, low-cost, and capacity for mass production. Furthermore, they are environmentally friendly. Excellent luminescence and charge transport properties of QDs led to their application in QD-based light-emitting diodes (LEDs), which have attracted considerable attention in display and solid-state lighting applications. In this review, we discuss the applications of QDs which are used on color conversion filter that exhibit high efficiency in white LEDs, full-color micro-LED devices, and liquid-type structure devices, among others. Furthermore, we discuss different QD printing processes and coating methods to achieve the full-color micro-LED. With the rise in popularity of wearable and see-through red, green, and blue (RGB) full-color displays, the flexible substrate is considered as a good potential candidate. The anisotropic conductive film method provides a small controllable linewidth of electrically conductive particles. Finally, we discuss the advanced application for flexible full-color and highly efficient QD micro-LEDs. The general conclusion of this study also involves the demand for a more straightforward QD deposition technique, whose breakthrough is expected.