Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning.

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Energy-efficient high-fidelity image reconstruction with memristor arrays for medical diagnosis.

Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

Concealable physically unclonable function chip with a memristor array.

A physically unclonable function (PUF) is a creditable and lightweight solution to the mistrust in billions of Internet of Things devices. Because of this remarkable importance, PUF need to be immune to multifarious attack means. Making the PUF concealable is considered an effective countermeasure but it is not feasible for existing PUF designs. The bottleneck is finding a reproducible randomness source that supports repeatable concealment and accurate recovery of the PUF data. In this work, we experimentally demonstrate a concealable PUF at the chip level with an integrated memristor array and peripherals. The correlated filamentary switching characteristic of the hafnium oxide (HfOx)-based memristor is used to achieve PUF concealment/recovery with SET/RESET operations efficiently. PUF recovery with a zero-bit error rate and remarkable attack resistance are achieved simultaneously with negligible circuit overhead. This concealable PUF provides a promising opportunity to build memristive hardware systems with effective security in the near future.

Memristor-based analogue computing for brain-inspired sound localization with in situ training.

The human nervous system senses the physical world in an analogue but efficient way. As a crucial ability of the human brain, sound localization is a representative analogue computing task and often employed in virtual auditory systems. Different from well-demonstrated classification applications, all output neurons in localization tasks contribute to the predicted direction, introducing much higher challenges for hardware demonstration with memristor arrays. In this work, with the proposed multi-threshold-update scheme, we experimentally demonstrate the in-situ learning ability of the sound localization function in a 1K analogue memristor array. The experimental and evaluation results reveal that the scheme improves the training accuracy by ∼45.7% compared to the existing method and reduces the energy consumption by ∼184× relative to the previous work. This work represents a significant advance towards memristor-based auditory localization system with low energy consumption and high performance.

Rotating neurons for all-analog implementation of cyclic reservoir computing.

Hardware implementation in resource-efficient reservoir computing is of great interest for neuromorphic engineering. Recently, various devices have been explored to implement hardware-based reservoirs. However, most studies were mainly focused on the reservoir layer, whereas an end-to-end reservoir architecture has yet to be developed. Here, we propose a versatile method for implementing cyclic reservoirs using rotating elements integrated with signal-driven dynamic neurons, whose equivalence to standard cyclic reservoir algorithm is mathematically proven. Simulations show that the rotating neuron reservoir achieves record-low errors in a nonlinear system approximation benchmark. Furthermore, a hardware prototype was developed for near-sensor computing, chaotic time-series prediction and handwriting classification. By integrating a memristor array as a fully-connected output layer, the all-analog reservoir computing system achieves 94.0% accuracy, while simulation shows >1000× lower system-level power than prior works. Therefore, our work demonstrates an elegant rotation-based architecture that explores hardware physics as computational resources for high-performance reservoir computing.

Multichannel parallel processing of neural signals in memristor arrays.

Fully implantable neural interfaces with massive recording channels bring the gospel to patients with motor or speech function loss. As the number of recording channels rapidly increases, conventional complementary metal-oxide semiconductor (CMOS) chips for neural signal processing face severe challenges on parallelism scalability, computational cost, and power consumption. In this work, we propose a previously unexplored approach for parallel processing of multichannel neural signals in memristor arrays, taking advantage of their rich dynamic characteristics. The critical information of neural signal waveform is extracted and encoded in the memristor conductance modulation. A signal segmentation scheme is developed to adapt to device variations. To verify the fidelity of the processed results, seizure prediction is further demonstrated, with high accuracy above 95% and also more than 1000× improvement in power efficiency compared with CMOS counterparts. This work suggests that memristor arrays could be a promising multichannel signal processing module for future implantable neural interfaces.

Neural signal analysis with memristor arrays towards high-efficiency brain-machine interfaces.

Brain-machine interfaces are promising tools to restore lost motor functions and probe brain functional mechanisms. As the number of recording electrodes has been exponentially rising, the signal processing capability of brain-machine interfaces is falling behind. One of the key bottlenecks is that they adopt conventional von Neumann architecture with digital computation that is fundamentally different from the working principle of human brain. In this work, we present a memristor-based neural signal analysis system, where the bio-plausible characteristics of memristors are utilized to analyze signals in the analog domain with high efficiency. As a proof-of-concept demonstration, memristor arrays are used to implement the filtering and identification of epilepsy-related neural signals, achieving a high accuracy of 93.46%. Remarkably, our memristor-based system shows nearly 400× improvements in the power efficiency compared to state-of-the-art complementary metal-oxide-semiconductor systems. This work demonstrates the feasibility of using memristors for high-performance neural signal analysis in next-generation brain-machine interfaces.

Can pattern and depth of invasion predict lymph node relapse and prognosis in tongue squamous cell carcinoma.

BACKGROUND: Tongue squamous cell carcinoma (TSCC) is a special type of oral cancer. Cervical lymph node relapse may occur in a large percentage of TSCC patients, which usually indicates poor prognosis. In this cohort study, we focused on the predictive value of the pathological features on cervical lymph node relapse and TSCC prognosis (disease free survival). METHODS: One hundred forty-one TSCC patients staged as T1-2N0 were enrolled and categorized. Subjects were followed-up for 60 months. Univariate analysis was performed with Chi-square test for cervical lymph node relapse and Kaplan-Meier survival analysis and log rank P value for patient prognosis; multivariate analysis was also utilized with Cox regression. RESULTS: In univariate analysis, trabes growth pattern, depth of invasion greater than 4 mm, poor pathological differentiation and neurovascular invasion were considered as risk factors for cervical lymph node relapse and poor prognosis. In multivariate analysis, only patients with trabes growth pattern in the invasive front or depth of invasion larger than 4 mm had a higher risk of metastasis. Elder age group and trabes growth pattern of invasive front were considered as predictors of poor prognosis. Bad habits of smoking and alcohol consumption were related to the higher risk of metastasis. CONCLUSION: Trabes growth pattern of invasive front was a potent risk factor for TSCC cervical lymph node relapse and indicated poor prognosis. Preventive therapy including selective neck dissection was thus suggested for certain patients. TRIAL REGISTRATION: Not applicable.