Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication.

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

A Platform for Mechano(-Electrical) Characterization of Free-Standing Micron-Sized Structures and Interconnects.

A device for studying the mechanical and electrical behavior of free-standing micro-fabricated metal structures, subjected to a very large deformation, is presented in this paper. The free-standing structures are intended to serve as interconnects in high-density, highly stretchable electronic circuits. For an easy, damage-free handling and mounting of these free-standing structures, the device is designed to be fabricated as a single chip/unit that is separated into two independently movable parts after it is fixed in the tensile test stage. Furthermore, the fabrication method allows for test structures of different geometries to be easily fabricated on the same substrate. The utility of the device has been demonstrated by stretching the free-standing interconnect structures in excess of 1000% while simultaneously measuring their electrical resistance. Important design considerations and encountered processing challenges and their solutions are discussed in this paper.