Reliable metal-graphene contact formation process flows in a CMOS-compatible environment.

The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene-metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8'' wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal-graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω µm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing.

Influence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene.

One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.

High-Mobility Epitaxial Graphene on Ge/Si(100) Substrates.

Graphene was shown to reveal intriguing properties of its relativistic two-dimensional electron gas; however, its implementation to microelectronic applications is missing to date. In this work, we present a comprehensive study of epitaxial graphene on technologically relevant and in a standard CMOS process achievable Ge(100) epilayers grown on Si(100) substrates. Crystalline graphene monolayer structures were grown by means of chemical vapor deposition (CVD). Using angle-resolved photoemission spectroscopy and in situ surface transport measurements, we demonstrate their metallic character both in momentum and real space. Despite numerous crystalline imperfections, e.g., grain boundaries and strong corrugation, as compared to epitaxial graphene on SiC(0001), charge carrier mobilities of 1 × 104 cm2/Vs were obtained at room temperature, which is a result of the quasi-charge neutrality within the graphene monolayers on germanium and not dependent on the presence of an interface oxide. The interface roughness due to the facet structure of the Ge(100) epilayer, formed during the CVD growth of graphene, can be reduced via subsequent in situ annealing up to 850 °C coming along with an increase in the mobility by 30%. The formation of a Ge(100)-(2 × 1) structure demonstrates the weak interaction and effective delamination of graphene from the Ge/Si(100) substrate.

Metal-Free CVD Graphene Synthesis on 200 mm Ge/Si(001) Substrates.

Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH4 as carbon source on epitaxial Ge(100) layers, which were grown on Si(100), prior to the graphene synthesis. Graphene layer with the 2D/G ratio ∼3 and low D mode (i.e., low concentration of defects) was measured over the entire 200 mm wafer by Raman spectroscopy. A typical full-width-at-half-maximum value of 39 cm-1 was extracted for the 2D mode, further indicating that graphene of good structural quality was produced. The study also revealed that the lack of interfacial oxide correlates with superior properties of graphene. In order to evaluate electrical properties of graphene, its 2 × 2 cm2 pieces were transferred onto SiO2/Si substrates from Ge/Si wafers. The extracted sheet resistance and mobility values of transferred graphene layers were ∼1500 ± 100 Ω/sq and µ ≈ 400 ± 20 cm2/V s, respectively. The transferred graphene was free of metallic contaminations or mechanical damage. On the basis of results of DFT calculations, we attribute the high structural quality of graphene grown by CVD on Ge to hydrogen-induced reduction of nucleation probability, explain the appearance of graphene-induced facets on Ge(001) as a kinetic effect caused by surface step pinning at linear graphene nuclei, and clarify the orientation of graphene domains on Ge(001) as resulting from good lattice matching between Ge(001) and graphene nucleated on such nuclei.