Interface Trap-Induced Temperature Dependent Hysteresis and Mobility in ß-Ga2O3 Field-Effect Transistors.

Interface traps between a gate insulator and beta-gallium oxide (ß-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20-300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges' trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

Electrical Properties of Top-Gate ß-Ga2O3 Nanomembrane Metal-Semiconductor Field-Effect Transistor.

We fabricate top-gate ß-Ga2O3 nanomembrane metal-semiconductor field-effect transistor (MESFET) using a mechanical exfoliation method, and investigate its electrical performance. The Schottky contact between top-gate metal and ß-Ga2O3 (100) channel is evaluated by characterizing properties of Schottky barrier diode, exhibiting an on/off ratio of ~106, an ideality factor of 2.8 and a turn-on voltage of 1.1 V. The proposed top-gate ß-Ga2O3 nanomembrane MESFET exhibits maximum transconductance of ~0.23 mS/mm, field-effect mobility of 1.2 cm²/V·s at VDS = 1 V and subthreshold slope (SS) of 180 mV/dec with high on/off ratio of >107. These results suggest that ß-Ga2O3 nanomembrane MESFET could be a promising component toward ß-Ga2O3-based high power device applications.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS2 Transistors.

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Thickness-Dependent Electrical Properties of MoS2 Field-Effect Transistors Fabricated on Sol-Gel Prepared AlOX Layer.

Solution-processed high-k oxide layer, which is typically deposited using atomic layer deposition (ALD), has been proposed and recently demonstrated on molybdenum disulfide (MoS2) field-effect transistors (FETs). In this report, we statistically investigate electrical performance of multilayer MoS2 FETs fabricated on sol-gel AlOX gate-dielectric. More than 10 sample devices with different MoS2 thickness are characterized and compared. For electrical parameters extraction, Y -function method is adopted in order to minimize S/D electrode contact-induced variations. In spite of the relatively rougher surface of the sol-gel AlOX film, no significant difference of electrical performance is observed. The sol-gel prepared AlOX can be considered as a promising high-k gate dielectric for high-performance large-area transistion metal dichalcogenides (TMDs) devices fabrication.