High-performance GeSi/Ge multi-quantum well photodetector on a Ge-buffered Si substrate.

This work demonstrates a high-performance photodetector with a 4-cycle Ge0.86Si0.14/Ge multi-quantum well (MQW) structure grown by reduced pressure chemical vapor deposition techniques on a Ge-buffered Si (100) substrate. At -1 V bias, the dark current density of the fabricated PIN mesa devices is as low as 3 mA/cm2, and the optical responsivities are 0.51 and 0.17 A/W at 1310 and 1550 nm, respectively, corresponding to the cutoff wavelength of 1620 nm. At the same time, the device has good high-power performance and continuous repeatable light response. On the other hand, the temperature coefficient of resistance (TCR) of the device is as high as -5.18%/K, surpassing all commercial thermal detectors. These results indicate that the CMOS-compatible and low-cost Ge0.86Si0.14/Ge multilayer structure is promising for short-wave infrared and uncooled infrared imaging.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Indium doping-assisted monolayer Ga2O3 exfoliation for performance-enhanced MOSFETs.

Monolayer (ML) Ga2O3 with outstanding properties is promising for advanced nanodevice applications; however, its high exfoliation energy makes obtaining it challenging. In this study, we propose a more efficient solution to obtain ML Ga2O3 by exfoliation from indium-doped bulk ß-Ga2O3. The exfoliation efficiency with the assistance of In-doping and the doping influence on the stability and structural and electronic properties of ML Ga2O3 are systematically studied using first-principles calculations. The exfoliation energy of ML Ga2O3 is found to be reduced by 28% and is of the same order of magnitude as that of typical van der Waals (vdWs) 2D materials. Besides, excellent stability is preserved for ML Ga2O3 at extremely high In doping concentration by phonon spectrum and ab initio molecular dynamics inspections. The bandgap of ML Ga2O3 decreases from 4.88 to 4.25 eV with increased In concentration, and the modification of the VBM converts ML Ga2O3 to a direct bandgap semiconductor. With the suppression of ZA mode phonon scattering, the pristine and In-doped ML Ga2O3 exhibit high electron mobility, whereas the strong electron-phonon coupling (EPC) effect significantly decreases the hole mobility. Finally, the transfer characteristics of 5 nm MOSFETs based on the pristine and In-doped ML Ga2O3 with varied In concentrations are simulated based on the non-equilibrium Green's function (NEGF) formalism. The Ion for HP has a maximum of 3060 µA µm-1 at In doping concentration of 5% and is triple that of the pristine ML Ga2O3 for LP at In doping concentration of 20%. The FOMs of n-type MOSFETs based on the In-doped ML Ga2O3 and typical 2D materials are compared and shows huge potential for sub-5 nm applications. Our study applies a new strategy for obtaining ML Ga2O3 and can also improve the device performance at the same time.

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region.

Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, which will boost LiDAR applications. Although Si APDs have already been commercialized, their spectral region is very limited in many applications. Therefore, it is urgently demanded that the spectral region APDs be extended to the short-wavelength infrared (SWIR) region, which means better atmospheric transmission, a lower solar radiation background, a higher laser eye safety threshold, etc. Up until now, both Ge (GeSn) and InGaAs were employed as the SWIR absorbers. The aim of this review article is to provide a full understanding of Ge(GeSn) and InGaAs for PDs, with a focus on APD operation in the SWIR spectral region, which can be integrated onto the Si platform and is potentially compatible with CMOS technology.

First-Principles-Based Quantum Transport Simulations of High-Performance and Low-Power MOSFETs Based on Monolayer Ga2O3.

The electronic properties of monolayer (ML) Ga2O3 and transport properties of ML Ga2O3-based n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated by first-principles calculations under the framework of density functional theory (DFT) coupled with the nonequilibrium Green's function (NEGF) formalism. The results show that ML Ga2O3 has a quasi-direct band gap of 4.92 eV, and the x- and y-directed electron mobilities are 1210 and 816 cm2 V-1 s-1 at 300 K, respectively, under the full consideration of phonon scattering. The electron-phonon scattering mechanism shows a temperature-dependent behavior, with the acoustic modes dominating below 300 K and optical modes dominating above 300 K. At a gate length of Lg = 5 nm, the on-current of ML Ga2O3 n-MOSFET for high-performance (HP) application is 2890 µA/µm, which is more than those of the most reported two-dimensional (2D) materials. The delay time as well as the power delay product of ML Ga2O3 MOSFETs can meet the demands of the latest International Technology Roadmap for Semiconductors (ITRS) for HP and low-power (LP) applications until Lg is less than 4 and 5 nm, respectively. Through underlap structure and doping optimization strategies, ML Ga2O3 n-MOSFET can further fulfill the ITRS requirements for 1 nm. At last, we compare the performance of the 32-bit arithmetic logic unit (ALU) built on ML Ga2O3 MOSFETs with the recently reported beyond-CMOS devices. Our results indicate that ML Ga2O3 can serve as a promising channel material in the post-silicon era.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm-2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 µm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-µm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III-V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.

Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer. No patterned substrate or sophisticated superlattice defect-filtering layer was involved. Thanks to the improved quality of the comprehensively modified GaAs crystal with low defect density, the room temperature emission wavelength of this laser was allocated at 1320 nm, with a threshold current density of 24.4 A/cm-2 per layer and a maximum single-facet output power reaching 153 mW at 10 °C. The maximum operation temperature reaches 80 °C. This work provides a feasible and promising proposal for the integration of an efficient O-band laser with a standard Si platform in the near future.

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm-2 in a globally grown Ge layer to 3.2 × 105 cm-2 for a single-step SEG and to 2.84 × 105 cm-2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications.

GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285-320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm-2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was -0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm-2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski-Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it's threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm-2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

High Performance p-i-n Photodetectors on Ge-on-Insulator Platform.

In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 µm, the dark current at -1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at -1 V are as low as 1.79 mA/cm2 and 0.34 µA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.

Nanoscale growth of a Sn-guided SiGeSn alloy on Si (111) substrates by molecular beam epitaxy.

Here, SiGeSn nanostructures were grown via molecular beam epitaxy on a Si (111) substrate with the assistance of Sn droplets. Owing to the thermal effect and the compressive strain induced by a lattice mismatch, Si and Sn atoms were successfully incorporated into the Ge matrix during the Sn-guided Ge deposition process. A low growth temperature of 350 °C produced a variety of SiGeSn nanostructures of different sizes, attributed to the variation of the initial Sn droplet size. Using energy-dispersive X-ray spectroscopy, the Sn, Si and Ge contents of a defect-free SiGeSn nanoisland were approximately determined to be 0.05, 0.09 and 0.86, respectively. Furthermore, as the growth temperature increased past 600 °C, the growth direction of the nanostructure was changed thermally from out-of-plane to in-plane. Meanwhile, the stacked SiGeSn nanowires grown along the 〈112〉 direction remained defect-free, though some threading dislocations were observed in the smooth SiGeSn nanowires along the 〈110〉 direction. These results offer a novel method to grow Si-based SiGeSn nanostructures while possessing important implications for fabricating further optoelectronic devices.

High-quality GeSn Layer with Sn Composition up to 7% Grown by Low-temperature Magnetron Sputtering for Optoelectronic Application.

In this paper, a high-quality sputtered-GeSn layer on Ge (100) with a Sn composition up to 7% was demonstrated. The crystallinity of the GeSn layer was investigated via high-resolution X-ray diffraction (HR-XRD) and the strain relaxation degree of the GeSn layer was evaluated to be approximately 50%. A novel method was also proposed to evaluate the averaged threading dislocation densities (TDDs) in the GeSn layer, which was obtained from the rocking curve of GeSn layer along the (004) plane. The photoluminescence (PL) measurement result shows the significant optical emission (1870 nm) from the deposited high-quality GeSn layer. To verify whether our deposited GeSn can be used for optoelectronic devices, we fabricated the simple vertical p-i-n diode, and the room temperature current-voltage (I-V) characteristic was obtained. Our work paves the way for future sputtered-GeSn optimization, which is critical for optoelectronic applications.