ABSTRACT
We introduce a new design space for optimizing III-V devices monolithically grown on Silicon substrates by extending the concept of nano-ridge engineering from binary semiconductors such as GaAs, InAs and GaSb to the ternary alloy InGaAs. This allows controlling the fundamental lattice constant of the fully relaxed ternary nano-ridge which thereby serves as a tunable base for the integration of diverse device hetero-layers. To demonstrate the flexibility of this approach, we realized an O-band nano-ridge laser containing three In0.45Ga0.55As quantum wells, which are pseudomorphically strained to an In0.25Ga0.75As nano-ridge base. The demonstration of an optically pumped nano-ridge laser operating around 1300â nm underlines the potential of this cost-efficient and highly scalable integration approach for silicon photonics.
ABSTRACT
Nano-ridge engineering (NRE) is a novel method to monolithically integrate III-V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106âcm-2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices-consisting of several nano-ridges in parallel-were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III-V devices for hybrid III-V/CMOS technology for emerging RF applications.
ABSTRACT
Nowadays electron channeling contrast imaging (ECCI) is widely used to characterize crystalline defects on blanket semiconductors. Its further application in the semiconductor industry is however challenged by the emerging rise of nanoscale 3D heterostructures. In this study, an angular multi-segment detector is utilized in backscatter geometry to investigate the application of ECCI to the defect analysis of 3D semiconductor structures such as III/V nano-ridges. We show that a low beam energy of 5 keV is more favorable and that the dimension of 3D structures characterized by ECCI can be scaled down to ~ 28 nm. Furthermore, the impact of device edges on the collected ECCI image is investigated and correlated with tool parameters and cross-section profiles of the 3D structures. It is found that backscattered electrons (BSE) emitted from the device edge sidewalls and generating the bright edges (edge effects), share a similar angular distribution to those emitted from the surface. We show that the collection of low angle BSEs can suppressed the edge effects, however, at the cost of losing the defect contrast. A positive stage bias suppresses edge effects by removing the inelastically backscattered electrons from the sidewalls, but low loss BSEs from the sidewalls still contribute to the ECCI micrographs. On the other hand, if segments of an angular backscatter (ABS) detector are properly aligned with the nano-ridges, BSEs emitted from the sidewall and the surface can be separated, thus leading to the completely absence of one bright edge on the surface without compromise of the defect contrast. The merging of two such ECCI images reveals the nano-ridge surface without edge effects.