ABSTRACT
The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying -45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.
ABSTRACT
A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-µm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 µm × 40 µm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 µW per pixel.
