Local mapping of surface potential in pentacene thin film under gate bias voltage obtained by scanning kelvin probe microscopy.

We report the local surface potential mapping of pentacene film prepared by physical vapor deposition with scanning kelvin probe microscopy where the sample is scanned under different gate voltages. Surface topography and the corresponding potential maps were obtained simultaneously. Spatial distribution of the surface potential at a low gate voltage is clearly correlated with topographic features. A lower electrostatic potential was measured at the grain boundaries (GBs), suggesting that GBs behave as hole traps. This observation is bolstered by conductive atomic force microscopy (C-AFM) data, which reveals a higher conductivity within the grains as opposed to the GBs. An increase in gate voltage minimizes the potential differences at the grain and GBs, suggesting a modification in trap occupancy. We expect that these experimental results, along with existing theories, will provide a better understanding of the microstructural-electrical properties of pentacene film. RESEARCH HIGHLIGHTS: Local surface potential mapping of pentacene film with scanning kelvin probe microscopy. Correlation between the surface potential map and topography at a low gate voltage. Decrease of the potential distribution inhomogeneity by the gate voltage increasement. Higher conductivity at inner grain than grain boundary in conductive atomic force microscopy.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors.

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.