Memristively programmable transistors.

When designing the gate-dielectric of a floating-gate-transistor, one must make a tradeoff between the necessity of providing an ultra-small leakage current behavior for long state retention, and a moderate to high tunneling-rate for fast programming speed. Here we report on a memristively programmable transistor that overcomes this tradeoff. The operation principle is comparable to floating-gate-transistors, but the advantage of the analyzed concept is that ions instead of electrons are used for programming. Since the mass of ions is significantly larger than the effective mass of electrons, gate-dielectrics with higher leakage current levels can be used. We demonstrate the practical feasibility of the device using a proof-of-concept study based on a micrometer-sized thin-film transistor and LT-Spice simulations of 32 nm transistors. Memristively programmable transistors have the potential of high programming endurance and retention times, fast programming speeds, and high scalability.

Capacity based nondestructive readout for complementary resistive switches.

Complementary resistive switches (CRS) were recently suggested to solve the sneak path problem of larger passive memory arrays. CRS cells consist of an antiserial setup of two bipolar resistive switching cells. The conventional destructive readout for CRS cells is based on a current measurement which makes a considerable call on the switching endurance. Here, we report a new approach for a nondestructive readout (NDRO) based on a capacity measurement. We suggest a concept of an alternative setup of a CRS cell in which both resistive switching cells have similar switching properties but are distinguishable by different capacities. The new approach has the potential of an energy saving and fast readout procedure without decreasing cycling performance and is not limited by the switching kinetics for integrated passive memory arrays.