ABSTRACT
We report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by a block copolymer self-assembly process. Optimized surface functionalization provides stacking structures of Si-containing block copolymer thin films to generate uniform memristor device structures. Both the silicon oxide film and nanodot memristors, which were formed by the plasma oxidation of the self-assembled block copolymer thin films, presented unipolar switching behaviors with appropriate set and reset voltages for resistive memory applications. This approach offers a very convenient pathway to fabricate ultrahigh-density resistive memory devices without relying on high-cost lithography and pattern-transfer processes.
Subject(s)
Crystallization/methods , Electronics/instrumentation , Graphite/chemistry , Metals/chemistry , Microelectrodes , Nanostructures/chemistry , Silicon Dioxide/chemistry , Electric Impedance , Equipment Design , Equipment Failure Analysis , Macromolecular Substances/chemistry , Materials Testing , Molecular Conformation , Nanostructures/ultrastructure , Particle Size , Surface PropertiesABSTRACT
In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.
ABSTRACT
The sub-50 nm templates are successfully fabricated using hydrogen silsesquioxane (HSQ) and silicon nitride on silicon substrate. The HSQ template is directly patterned by e-beam direct writing. The cured HSQ pattern is used for the template of nanoimprint process. The silicon nitride template is reactively ion etched by ZEP resist mask pattern which is prepared by e-beam direct writing using ZEP resist. The line widths of HSQ templates and ZEP patterns after developments are between 22-30 nm and 24-30 nm, respectively. The line width of silicon nitride templates without performing descum is same as that of the ZEP pattern but shows a rough surface. When plasma descum was performed before RIE, the line width of silicon nitride templates increased from 27 nm to 35 nm and has a clean surface. The HSQ template fabrication results in this study will be promise for sub-nm imprint process.
