Editorial for the Special Issue "Amorphous and Nanocrystalline Semiconductors: Selected Papers from ICANS 29".

The 29th International Conference on Amorphous and Nanocrystalline Semiconductors served as a continuation of the biennial conference that has been held since 1965 [...].

Synthesis and characterization of Ge-core/a-Si-shell nanowires with conformal shell thickness deposited after gold removal for high-mobility p-channel field-effect transistors.

Ge-core/a-Si-shell nanowires were synthesized in three consecutive steps. Nominally undoped crystalline Ge nanowires were first grown using a vapor-liquid-solid growth mechanism, followed by gold catalyst removal in an etching solution and deposition of a thin layer of amorphous silicon on the nanowire surface using a chemical vapor deposition method. Catalyst removal is necessary to avoid catalyst melting during temperature increase prior to a-Si shell deposition. Field effect transistors based on Ge-core/a-Si-shell nanowires exhibited p-channel depletion-mode characteristics as a result of free hole accumulation in the Ge channel. Scaled on-currents and transconductances up to 3.1 mA µm-1 and 4.3 mS µm-1, respectively, as well as on/off ratios and field-effect hole mobilities up to 102 and 664 cm2 V-1 s-1, respectively, were obtained for these Ge-core/a-Si-shell nanowire FETs. The minimum subthreshold slope was measured to be 300 mV dec-1. The present work also demonstrates for the first time the conductance quantization in one-dimensional Ge-core/a-Si-shell nanowires at low temperatures. The quantization of conductances at discrete values of G 0 = 2e 2/h at low temperatures suggests that our Ge-core/a-Si-shell nanowires are multi-mode ballistic conductors with a mean-free-path up to 500 nm. The results provided here are relevant for the synthesis of high-quality Ge-core/Si-shell nanowires for high-mobility devices with transparent contacts to hole carriers.

An electronic synaptic device based on HfO2TiOx bilayer structure memristor with self-compliance and deep-RESET characteristics.

We reported on a Ti/HfO2/TiOx/Pt memristor with self-compliance, deep-RESET characteristics and excellent switching performance, including ultrafast program/erase speed (10 ns), a large memory window (103) and good pulse endurance (107 cycles). The self-compliance and deep-RESET characteristics are beneficial for protecting the device from permanent breakdown in both SET and RESET processes especially under the pulse operation mode. In addition to bistable state switching, we also achieved multiple or even continuous conductance state switching under a DC sweep and a pulse-train operation mode in the Ti/HfO2/TiOx/Pt memristor, which can be seen as a substitution of a biological synapse. The capability of continuous modulation conductance (synaptic weight) in the Ti/HfO2/TiOx/Pt memristor was investigated and the potentiation and depression characteristics of the synaptic weight could be precisely tuned by the number or amplitude of the input pulse-train. Moreover, clear experimental evidence of short-term plasticity (STP) and long-term plasticity (LTP) in a single memristor was also demonstrated. Increasing the pulse amplitude or width, or decreasing the interval of two adjacent pulses of the input pulse-train resulted in the memristor behavior transitioning from STP to LTP. The realization of those important synaptic functions in the Ti/HfO2/TiOx/Pt memristor may be suitable for applications in artificial neural systems.

A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9.

The isolation of qubits from noise sources, such as surrounding nuclear spins and spin-electric susceptibility 1-4 , has enabled extensions of quantum coherence times in recent pivotal advances towards the concrete implementation of spin-based quantum computation. In fact, the possibility of achieving enhanced quantum coherence has been substantially doubted for nanostructures due to the characteristic high degree of background charge fluctuations 5-7 . Still, a sizeable spin-electric coupling will be needed in realistic multiple-qubit systems to address single-spin and spin-spin manipulations 8-10 . Here, we realize a single-electron spin qubit with an isotopically enriched phase coherence time (20 µs) 11,12 and fast electrical control speed (up to 30 MHz) mediated by extrinsic spin-electric coupling. Using rapid spin rotations, we reveal that the free-evolution dephasing is caused by charge noise-rather than conventional magnetic noise-as highlighted by a 1/f spectrum extended over seven decades of frequency. The qubit exhibits superior performance with single-qubit gate fidelities exceeding 99.9% on average, offering a promising route to large-scale spin-qubit systems with fault-tolerant controllability.

A fault-tolerant addressable spin qubit in a natural silicon quantum dot.

Fault-tolerant quantum computing requires high-fidelity qubits. This has been achieved in various solid-state systems, including isotopically purified silicon, but is yet to be accomplished in industry-standard natural (unpurified) silicon, mainly as a result of the dephasing caused by residual nuclear spins. This high fidelity can be achieved by speeding up the qubit operation and/or prolonging the dephasing time, that is, increasing the Rabi oscillation quality factor Q (the Rabi oscillation decay time divided by the π rotation time). In isotopically purified silicon quantum dots, only the second approach has been used, leaving the qubit operation slow. We apply the first approach to demonstrate an addressable fault-tolerant qubit using a natural silicon double quantum dot with a micromagnet that is optimally designed for fast spin control. This optimized design allows access to Rabi frequencies up to 35 MHz, which is two orders of magnitude greater than that achieved in previous studies. We find the optimum Q = 140 in such high-frequency range at a Rabi frequency of 10 MHz. This leads to a qubit fidelity of 99.6% measured via randomized benchmarking, which is the highest reported for natural silicon qubits and comparable to that obtained in isotopically purified silicon quantum dot-based qubits. This result can inspire contributions to quantum computing from industrial communities.

Deionization of Dopants in Silicon Nanofilms Even with Donor Concentration of Greater than 10(19) cm(-3).

Understanding the dopant properties in heavily doped nanoscale semiconductors is essential to design nanoscale devices. We report the deionization or finite ionization energy of dopants in silicon (Si) nanofilms with dopant concentration (ND) of greater than 10(19) cm(-3), which is in contrast to the zero ionization energy (ED) in bulk Si at the same ND. From the comparison of experimentally observed and theoretically calculated ED, we attribute the deionization to the suppression of metal-insulator transition in highly doped nanoscale semiconductors in addition to the quantum confinement and the dielectric mismatch, which greatly increase ED in low-doped nanoscale semiconductors. Thus, for nanoscale transistors, ND should be higher than that estimated from bulk Si dopant properties in order to reduce their resistivity by the metal-insulator transition.

Germanium nanowires with 3-nm-diameter prepared by low temperature vapour-liquid-solid chemical vapour deposition.

We report the growth of germanium nanowires (Ge NWs) with single-step temperature method via vapour-liquid-solid (VLS) mechanism in the low pressure chemical vapour deposition (CVD) reactor at 300 degrees C, 280 degrees C, and 260 degrees C. The catalyst used in our experiment was Au nanoparticles with equivalent thicknesses of 0.1 nm (average diameter approximately 3 nm), 0.3 nm (average diameter approximately 4 nm), 1 nm (average diameter approximately 6 nm), and 3 nm (average diameter approximately 14 nm). The Gibbs-Thomson effect was used to explain our experimental results. The Ge NWs grown at 300 degrees C tend to have tapered structure while the Ge NWs grown at 280 degrees C and 260 degrees C tend to have straight structure. Tapering was caused by the uncatalysed deposition of Ge atoms via CVD mechanism on the sidewalls of nanowire and significantly minimised at lower temperature. We observed that the growth at lower temperature yielded Ge NWs with smaller diameter and also observed that the diameter and length of Ge NWs increases with the size of Au nanoparticles for all growth temperatures. For the same size of Au nanoparticles, Ge NWs tend to be longer with a decrease in temperature. The Ge NWs grown at 260 degrees C from 0.1-nm-thick Au had diameter as small as approximately 3 nm, offering an opportunity to fabricate high-performance p-type ballistic Ge NW transistor, to realise nanowire solar cell with higher efficiency, and also to observe the quantum confinement effect.

Silicon-on-insulator-based radio frequency single-electron transistors operating at temperatures above 4.2 K.

A radio frequency single-electron transistor (RF-SET) based on a silicon-on-insulator (SOI) substrate is demonstrated to operate successfully at temperatures above 4.2 K. The SOI SET was fabricated by inducing lateral constrictions in doped SOI nanowires. The device structure was optimized to overcome the inherent drawback of high resistance with the SOI SETs. We performed temperature variation measurements after five thermal cyclings of the same sample to 4.2 K and found that the single-dot device transport characteristics are highly stable. The charge sensitivity was measured to be 36 microe(rms) Hz(-1/2) at 4.2 K, and the RF-SET operation was demonstrated up to 12.5 K for the first time. This work is an important prerequisite to realizing operation of RF-SETs at noncryogenic temperatures.