Advanced Graphene-Based Transparent Conductive Electrodes for Photovoltaic Applications.

New architectures of transparent conductive electrodes (TCEs) incorporating graphene monolayers in different configurations have been explored with the aim to improve the performance of silicon-heterojunction (SHJ) cell front transparent contacts. In SHJ technology, front electrodes play an important additional role as anti-reflectance (AR) coatings. In this work, different transparent-conductive-oxide (TCO) thin films have been combined with graphene monolayers in different configurations, yielding advanced transparent electrodes specifically designed to minimize surface reflection over a wide range of wavelengths and angles of incidence and to improve electrical performance. A preliminary analysis reveals a strong dependence of the optoelectronic properties of the TCEs on (i) the order in which the different thin films are deposited or the graphene is transferred and (ii) the specific TCO material used. The results shows a clear electrical improvement when three graphene monolayers are placed on top on 80-nm-thick ITO thin film. This optimum TCE presents sheet resistances as low as 55 Ω/sq and an average conductance as high as 13.12 mS. In addition, the spectral reflectance of this TCE also shows an important reduction in its weighted reflectance value of 2-3%. Hence, the work undergone so far clearly suggests the possibility to noticeably improve transparent electrodes with this approach and therefore to further enhance silicon-heterojunction cell performance. These results achieved so far clearly open the possibility to noticeably improve TCEs and therefore to further enhance SHJ contact-technology performance.

High-k gate stacks on low bandgap tensile strained Ge and GeSn alloys for field-effect transistors.

We present the epitaxial growth of Ge and Ge0.94Sn0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al2O3, 5 nm HfO2, or 1 nmAl2O3/4 nm HfO2, on strained Ge and strained Ge0.94Sn0.06. Experimental capacitance-voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations.