Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/µm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Aligned carbon nanotube-based electronics on glass wafer.

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.

Improving Carbon Nanotube-Based Radiofrequency Field-Effect Transistors by the Device Architecture and Doping Process.

The semiconducting carbon nanotube (CNT) has been considered a promising candidate for future radiofrequency (RF) electronics due to its excellent electrical properties of high mobility and small capacitance. After decades of development, great progress has been achieved on CNT-based RF field-effect transistors (FETs). However, almost all elevations are owing to advancement of the CNT materials and fabrication process, while the study of device architecture is seldom considered and reported. In this work, we innovatively combined device architecture and related doping processes to further optimize CNT-based RF FETs by guiding process or materials with collaborative optimization for the first time and explore their effect on device performance carefully and statistically. Based on more mature random-oriented CNT materials, we fabricated CNT-based RF FETs having three different gate positions of device architecture variation accompanied by suitable doping schemes. The optimized FETs obtained 2-3 times of current density (transconductance) and 1.3 times the cutoff frequency and maximum oscillation frequency compared with unoptimized devices at the same channel length. After transistor-level verification of effect, we further built a CNT RF amplifier and demonstrated almost 10 dB of transducer gain improvement operating at 8 GHz for X-band application. The achieved results from this work would help further improve CNT RF performance beyond the materials and process point of view.