Carbon nanotube computer.

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

Semiconducting single-walled carbon nanotubes (SWCNTs) have great potential of becoming the channel material for future thin-film transistor technology. However, an effective sorting technique is needed to obtain high-quality semiconducting SWCNTs for optimal device performance. In our previous work, we reported a dispersion technique for semiconducting SWCNTs that relies on regioregular poly(3-dodecylthiophene) (rr-P3DDT) to form hybrid nanostructures. In this study, we demonstrate the scalability of those sorted CNT composite structures to form arrays of TFTs using standard lithographic techniques. The robustness of these CNT nanostructures was tested with Raman spectroscopy and atomic force microscope images. Important trends in device properties were extracted by means of electrical measurements for different CNT concentrations and channel lengths (L(c)). A statistical study provided an average mobility of 1 cm(2)/V·s and I(on)/I(off) as high as 10(6) for short channel lengths (L(c) = 1.5 µm) with 100% yield. This highlights the effectiveness of this sorting technique and its scalability for large-scale, flexible, and transparent display applications.

Selective dispersion of high purity semiconducting single-walled carbon nanotubes with regioregular poly(3-alkylthiophene)s.

Conjugated polymers, such as polyfluorene and poly(phenylene vinylene), have been used to selectively disperse semiconducting single-walled carbon nanotubes (sc-SWNTs), but these polymers have limited applications in transistors and solar cells. Regioregular poly(3-alkylthiophene)s (rr-P3ATs) are the most widely used materials for organic electronics and have been observed to wrap around SWNTs. However, no sorting of sc-SWNTs has been achieved before. Here we report the application of rr-P3ATs to sort sc-SWNTs. Through rational selection of polymers, solvent and temperature, we achieved highly selective dispersion of sc-SWNTs. Our approach enables direct film preparation after a simple centrifugation step. Using the sorted sc-SWNTs, we fabricate high-performance SWNT network transistors with observed charge-carrier mobility as high as 12 cm(2) V(-1) s(-1) and on/off ratio of >10(6). Our method offers a facile and a scalable route for separating sc-SWNTs and fabrication of electronic devices.

Linear increases in carbon nanotube density through multiple transfer technique.

We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain-source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/µm, accompanied by an increase in drain-source CNFET current from 4.3 to 17.4 µA/µm.

The effect of amine protonation on the electrical properties of spin-assembled single-walled carbon nanotube networks.

Amine-terminated self-assembled monolayers (SAMs) have been shown to selectively adsorb semiconducting single-walled carbon nanotubes (sc-SWNTs). Previous studies have shown that when deposited by spin coating, the resulting nanotube networks (SWNTnts) can be strongly influenced by the charge state of the amine (primary, secondary, and tertiary). When the amine surfaces were exposed to varying pH solutions, the conductivity and overall quality of the resulting fabricated networks were altered. Atomic force microscopy (AFM) topography had shown that the density of the SWNTnts was reduced as the amine protonation decreased, indicating that the electrostatic attraction between the SWNTs in solution and the surface influenced the adsorption. Simultaneously, µ-Raman analysis had suggested that when exposed to more basic conditions, the resulting networks were enhanced with sc-SWNTs. To directly confirm this enhancement, Ti/Pd contacts were deposited and devices were tested in air. Key device characteristics were found to match the enhancement trends previously observed by spectroscopy. For the primary and secondary amines, on/off current ratios were commensurate with the Raman trends in metallic contribution, while no trends were observed on the tertiary amine (due to weaker interactions). Finally, differing SWNT solution volumes were used to compensate for adsorption differences and yielded identical SWNTnt densities on the various pH-treated samples to eliminate the influence of network density. These results further the understanding of the amine-SWNT interaction during the spin coating process. Overall, we provide a convenient route to provide SWNT-based TFTs with highly tunable electronic charge transport through better understanding of the influence of these specific interactions.

Solution assembly of organized carbon nanotube networks for thin-film transistors.

Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.