Toward a general-purpose analog VLSI neural network with on-chip learning.

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

A neural network learning algorithm tailored for VLSI implementation.

This paper describes concepts that optimize an on-chip learning algorithm for implementation of VLSI neural networks with conventional technologies. The network considered comprises an analog feedforward network with digital weights and update circuitry, although many of the concepts are also valid for analog weights. A general, semi-parallel form of perturbation learning is used to accelerate hidden-layer update while the infinity-norm error measure greatly simplifies error detection. Dynamic gain adaption, coupled with an annealed learning rate, produces consistent convergence and maximizes the effective resolution of the bounded weights. The use of logarithmic analog-to-digital conversion, during the backpropagation phase, obviates the need for digital multipliers in the update circuitry without compromising learning quality. These concepts have been validated through network simulations of continuous mapping problems.

New strategies for improving speech enhancement.

We describe two design strategies that could substantially improve the performance of speech enhancement systems. Results from a preliminary study of pulse recovery are presented to illustrate the potential benefits of such strategies. The first strategy is a direct application of a non-linear, adaptive signal processing approach for recovery of speech in noise. The second strategy optimizes performance by maximizing the enhancement system's ability to evoke target speech percepts. This approach may lead to better performance because the design is optimized on a measure directly related to the ultimate goal of speech enhancement: accurate communication of the speech percept. In both systems, recently developed 'neural network' learning algorithms can be used to determine appropriate parameters for enhancement processing.

A monolithic patch-clamping amplifier with capacitive feedback.

Patch-clamping is an established method for directly measuring ionic transport through cellular membranes with sufficient resolution to observe open/close transitions of individual channel molecules. This paper describes an alternative technique for patch-clamping which uses a capacitor as the transimpedance element. This approach eliminates bandwidth and saturation limitations experienced with resistive patch-clamping amplifiers. A complete monolithic design featuring an on-chip operational amplifier, a capacitor array with gain-ranging from 30 pF down to 0.03 pF, and reset and gain ranging switches has been fabricated using 5 microns CMOS technology. It is shown that the voltage noise of the CMOS operational amplifier limits the overall noise performance, but that performance competitive with conventional instruments can be achieved over a 10 kHz bandwidth, at least for small input capacitances (less than or equal to 5 pF). Results are presented along with an analysis and comparison of noise performance using both resistive and capacitive elements.