Roadmap on thermoelectricity.

The increasing energy demand and the ever more pressing need for clean technologies of energy conversion pose one of the most urgent and complicated issues of our age. Thermoelectricity, namely the direct conversion of waste heat into electricity, is a promising technique based on a long-standing physical phenomenon, which still has not fully developed its potential, mainly due to the low efficiency of the process. In order to improve the thermoelectric performance, a huge effort is being made by physicists, materials scientists and engineers, with the primary aims of better understanding the fundamental issues ruling the improvement of the thermoelectric figure of merit, and finally building the most efficient thermoelectric devices. In this Roadmap an overview is given about the most recent experimental and computational results obtained within the Italian research community on the optimization of composition and morphology of some thermoelectric materials, as well as on the design of thermoelectric and hybrid thermoelectric/photovoltaic devices.

Silicon Nanowires: A Breakthrough for Thermoelectric Applications.

The potentialities of silicon as a starting material for electronic devices are well known and largely exploited, driving the worldwide spreading of integrated circuits. When nanostructured, silicon is also an excellent material for thermoelectric applications, and hence it could give a significant contribution in the fundamental fields of energy micro-harvesting (scavenging) and macro-harvesting. On the basis of recently published experimental works, we show that the power factor of silicon is very high in a large temperature range (from room temperature up to 900 K). Combining the high power factor with the reduced thermal conductivity of monocrystalline silicon nanowires and nanostructures, we show that the foreseen figure of merit ZT could be very high, reaching values well above 1 at temperatures around 900 K. We report the best parameters to optimize the thermoelectric properties of silicon nanostructures, in terms of doping concentration and nanowire diameter. At the end, we report some technological processes and solutions for the fabrication of macroscopic thermoelectric devices, based on large numbers of silicon nanowire/nanostructures, showing some fabricated demonstrators.

Seebeck coefficient of silicon nanowire forests doped by thermal diffusion.

Thermoelectric generators made by large arrays of nanowires perpendicular to a silicon substrate, that is, so-called silicon nanowire forests are fabricated on large areas by an inexpensive metal-assisted etching technique. After fabrication, a thermal diffusion process is used for doping the nanowire forest with phosphorous. A suitable experimental technique has been developed for the measurement of the Seebeck coefficient under static conditions, and results are reported for different doping parameters. These results are in good agreement with numerical simulations of the doping process applied to silicon nanowires. These devices, based on doped nanowire forests, offer a possible route for the exploitation of the high power factor of silicon, which, combined with the very low thermal conductivity of nanostructures, will yield a high efficiency of the conversion of thermal to electrical energy.

On the mechanism ruling the morphology of silicon nanowires obtained by one-pot metal-assisted chemical etching.

One-pot Ag-assisted chemical etching (SACE) of silicon provides an effective, simple way to obtain Si nanowires (NWs) of potential interest for technological applications ranging from photovoltaics to thermoelectricity. The detailed mechanism ruling the process has not been yet fully elucidated, however. In this paper we report the results of an extended analysis of the interplay among doping level and type of silicon, nanowire nanomorphology and the parameters controlling the chemistry of the etching process. We provide evidence that the SACE mechanism entirely occurs at the interface between the etching solution and the Si substrate as a result of Si extrusion by sinking self-propelled Ag particles. Also, a rationale is advanced to explain the reported formation of (partially) porous NWs at high doping levels in both p- and n-type Si. A model not relying on the asserted formation of potential barriers enables to recover full consistency between SACE electrochemistry and the mechanism of formation of porous silicon in electrochemical cells.

High Power Thermoelectric Generator Based on Vertical Silicon Nanowires.

Thermoelectric generators, which convert heat directly into electrical power, have great potentialities in the energy harvesting field. The exploitation of these potentialities is limited by the materials currently used, characterized by good thermoelectric properties, but also by several drawbacks. This work presents a silicon-based thermoelectric generator, made of a large collection of heavily p-doped silicon nanostructures. This macroscopic device (area of several mm2) collects together the good thermoelectric features of silicon, in terms of high power factor, and a very reduced thermal conductivity, which resulted in being exceptionally low (1.8 W/(m K), close to the amorphous limit). The generated electrical power density is remarkably high for a Si-based thermoelectric generator, and it is suitable for scavenging applications which can exploit small temperature differences. A full characterization of the device (Seebeck coefficient, thermal conductivity, maximum power output) is reported and discussed.

Inkjet-printed graphene Hall mobility measurements and low-frequency noise characterization.

We report room temperature Hall mobility measurements, low temperature magnetoresistance analysis and low-frequency noise characterization of inkjet-printed graphene films on fused quartz and SiO2/Si substrates. We found that thermal annealing in vacuum at 450 °C is a necessary step in order to stabilize the Hall voltage across the devices, allowing their electrical characterization. The printed films present a minimum sheet resistance of 23.3 Ω sq-1 after annealing, and are n-type doped, with carrier concentrations in the low 1020 cm-3 range. The charge carrier mobility is found to increase with increasing film thickness, reaching a maximum value of 33 cm2 V-1 s-1 for a 480 nm-thick film printed on SiO2/Si. Low-frequency noise characterization shows a 1/f noise behavior and a Hooge parameter in the range of 0.1-1. These results represent the first in-depth electrical and noise characterization of transport in inkjet-printed graphene films, able to provide physical insights on the mechanisms at play.

Potentialities of silicon nanowire forests for thermoelectric generation.

Silicon is a material with very good thermoelectric properties, with regard to Seebeck coefficient and electrical conductivity. Low thermal conductivities, and hence high thermal to electrical conversion efficiencies, can be achieved in nanostructures, which are smaller than the phonon mean free path but large enough to preserve the electrical conductivity. We demonstrate that it is possible to fabricate a leg of a thermoelectric generator based on large collections of long nanowires, placed perpendicularly to the two faces of a silicon wafer. The process exploits the metal assisted etching technique which is simple, low cost, and can be easily applied to large surfaces. Copper can be deposited by electrodeposition on both faces, so that contacts can be provided, on top of the nanowires. Thermal conductivity of silicon nanowire forests with more than 107 nanowires mm-2 have been measured; the result is comparable with that achieved by several groups on devices based on few nanowires. On the basis of the measured parameters, numerical calculations of the efficiency of silicon-based thermoelectric generators are reported, and the potentialities of these devices for thermal to electrical energy conversion are shown. Criteria to improve the conversion efficiency are suggested and described.

Reliable Fabrication of Metal Contacts on Silicon Nanowire Forests.

We present a technique for the fabrication of an electrical (and thermal) contact on the top ends of a large number of vertical silicon nanowires, which are fabricated perpendicularly to a silicon wafer (silicon nanowire forest). The technique is based on electrochemical deposition of copper and has been developed on silicon nanowire forests, fabricated by metal assisted chemical etching. We demonstrate that copper grows selectively only on the top end of the silicon nanowires, forming a layer onto the top of the forest. The presence of a predeposited metal seed is fundamental for the selective growth, meanwhile the process is very strong with respect to other parameters, such as concentration of the electrolytic solution and current density, used during the metal deposition. Typical I-V characteristics of top-to-bottom conduction through silicon nanowire forests with different n-doping are shown and discussed.

Review of nanostructured devices for thermoelectric applications.

A big research effort is currently dedicated to the development of thermoelectric devices capable of a direct thermal-to-electrical energy conversion, aiming at efficiencies as high as possible. These devices are very attractive for many applications in the fields of energy recovery and green energy harvesting. In this paper, after a quick summary of the fundamental principles of thermoelectricity, the main characteristics of materials needed for high efficiency thermoelectric conversion will be discussed, and a quick review of the most promising materials currently under development will be given. This review paper will put a particular emphasis on nanostructured silicon, which represents a valid compromise between good thermoelectric properties on one side and material availability, sustainability, technological feasibility on the other side. The most important bottom-up and top-down nanofabrication techniques for large area silicon nanowire arrays, to be used for high efficiency thermoelectric devices, will be presented and discussed.

Seebeck coefficient of nanowires interconnected into large area networks.

We measured the macroscopic Seebeck coefficient of silicon nanowires (SiNWs), organized in a highly interconnected networks on large areas (order of mm(2)). The fabricated networks are very reliable with respect to random nanowire failure and are electrically and thermally equivalent to many SiNWs placed in parallel between the electrical contacts. The equivalent SiNWs have a macroscopic length of the order of millimeters and are very narrow (width smaller than 100 nm) so that they can be used to exploit thermoelectric properties at nanoscale for macroscopic electrical power generation and/or cooling. The measurement of the Seebeck coefficient S, facilitated by the macroscopic dimensions of the network, gives an insight into two questions, nanowire effective doping and carrier mobility, which are widely discussed in the literature. We found that the measured value of S is compatible with an effective doping that is higher than that of the original wafer. This higher doping is consistent with the value estimated from the measured electrical conductivity of the SiNWs with the assumption that the electron mobility inside the nanowire is equal to that of bulk silicon.

Correlation between surface stress and apparent Young's modulus of top-down silicon nanowires.

In this work, we report experimental evidence of surface stress effects on the mechanical properties of silicon nanostructures. As-fabricated, top-down silicon nanowires (SiNWs) are bent up without any applied force. This self-buckling is related to the surface relaxation that reaches an equilibrium with bulk deformation due to the material elasticity. We measure the SiNW self-deformation by atomic force microscopy (AFM), and we apply a simple physical model in order to give an estimation of the surface stress. If the equilibrium is altered by a nanoforce, applied by an AFM tip, nanowires find a new equilibrium condition bending down (mechanical bistability). In this work, for the first time, we report a clear and quantitative relationship between the SiNWs' apparent Young's modulus, measured by force-deflection spectroscopy, and the estimated value of surface stress, obtained by self-buckling measurements taking into account the Young's modulus of bulk silicon. This is an experimental confirmation that the surface stress is fundamental in determining mechanical properties of SiNWs, and that the elastic behavior of nanostructures strongly depends on their surfaces.

Fast, high bit number pattern generator for electron and ion beam lithographies.

High resolution electron and ion beam lithographies, fundamental tools for nanofabrication and nanotechnologies, require fast and high precision (high bit number) pattern generators. In the present work a solution for increasing the bit number, and preserving the speed of the system, is presented. A prototype with effective 18 bit resolution and with a write speed as fast as 10 MHz has been successfully tested: details of the adopted hardware solution are presented and described. This solution is very general and can be used in all those applications that require the generation of control voltages with an high bit number (high precision) at high speed, such as, for example, the scanning probe microscopy and nanomanipulation. Software solutions for increasing the data transfer efficiency are also presented; the aim of the adopted solutions is to preserve the flexibility and adaptability of the pattern generator to different writing strategies.