Improved Electrical Properties of AlGaN/GaN High-Electron-Mobility Transistors by In Situ Tailoring the SiNx Passivation Layer.

In situ metal-organic chemical vapor deposition growth of SiNx passivation layers is reported on AlGaN/GaN high-electron-mobility transistors (HEMTs) without surface damage. A higher SiNx growth rate, when produced by higher SiH4 reactant gas flow, enables faster lateral coverage and coalescence of the initial SiNx islands, thereby suppressing SiH4-induced III-nitride etching. The effect of in situ SiNx passivation on the structural properties of AlGaN/GaN HEMTs has been evaluated using high-resolution X-ray diffraction. Electrical properties of the passivated HEMTs were evaluated by clover-leaf van der Pauw Hall measurements. The key findings include (a) a correlation of constituent gas chemistry with SiNx stoichiometry, (b) the degree of suppression of strain relaxation in the barrier layer that can be optimized through the SiNx stoichiometry, and (c) optimum strain relaxation by tailoring the SiNx passivation layer stoichiometry that can result in near-ideal AlGaN/AlN/GaN interfaces. The latter is expected to reduce the carrier scatterings and improve electron mobility. Under optimized conditions, low sheet resistance and high electron mobility are obtained. At 10 K, a sheet resistance of 33 Ω/sq and a mobility of 16,500 cm2/V-s are achieved. At 300 K, the sheet resistance is 336 Ω/sq and mobility is 2020 cm2/V-s with a sheet charge density of 0.78 × 1013 cm-2.

Low Thermal Boundary Resistance Interfaces for GaN-on-Diamond Devices.

The development of GaN-on-diamond devices holds much promise for the creation of high-power density electronics. Inherent to the growth of these devices, a dielectric layer is placed between the GaN and diamond, which can contribute significantly to the overall thermal resistance of the structure. In this work, we explore the role of different interfaces in contributing to the thermal resistance of the interface of GaN/diamond layers, specifically using 5 nm layers of AlN, SiN, or no interlayer at all. Using time-domain thermoreflectance along with electron energy loss spectroscopy, we were able to determine that a SiN interfacial layer provided the lowest thermal boundary resistance (<10 m2K/GW) because of the formation of an Si-C-N layer at the interface. The AlN and no interlayer samples were observed to have TBRs greater than 20 m2K/GW as a result of a harsh growth environment that roughened the interface (enhancing phonon scattering) when the GaN was not properly protected.