CMOS Image Sensor for Broad Spectral Range with >90% Quantum Efficiency.

Even though the recent progress made in complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) has enabled numerous applications affecting our daily lives, the technology still relies on conventional methods such as antireflective coatings and ion-implanted back-surface field to reduce optical and electrical losses resulting in limited device performance. In this work, these methods are replaced with nanostructured surfaces and atomic layer deposited surface passivation. The results show that such surface nanoengineering applied to a commercial backside illuminated CIS significantly extends its spectral range and enhances its photosensitivity as demonstrated by >90% quantum efficiency in the 300-700 nm wavelength range. The surface nanoengineering also reduces the dark current by a factor of three. While the photoresponse uniformity of the sensor is seen to be slightly better, possible scattering from the nanostructures can lead to increased optical crosstalk between the pixels. The results demonstrate the vast potential of surface nanoengineering in improving the performance of CIS for a wide range of applications.

Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling.

A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging, the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor process. Using simulations, the noise performance of the pixel was determined as a function of the number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths and limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected performance of our first prototype device indicates that single-photon imaging is within reach and could enable ground-breaking performances in many scientific and industrial imaging applications.

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures.

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.