Toward a Brain-Neuromorphics Interface.

Brain-computer interfaces (BCIs) that enable human-machine interaction have immense potential in restoring or augmenting human capabilities. Traditional BCIs are realized based on complementary metal-oxide-semiconductor (CMOS) technologies with complex, bulky, and low biocompatible circuits, and suffer with the low energy efficiency of the von Neumann architecture. The brain-neuromorphics interface (BNI) would offer a promising solution to advance the BCI technologies and shape the interactions with machineries. Neuromorphic devices and systems are able to provide substantial computation power with extremely high energy-efficiency by implementing in-materia computing such as in situ vector-matrix multiplication (VMM) and physical reservoir computing. Recent progresses on integrating neuromorphic components with sensing and/or actuating modules, give birth to the neuromorphic afferent nerve, efferent nerve, sensorimotor loop, and so on, which has advanced the technologies for future neurorobotics by achieving sophisticated sensorimotor capabilities as the biological system. With the development on the compact artificial spiking neuron and bioelectronic interfaces, the seamless communication between a BNI and a bioentity is reasonably expectable. In this review, the upcoming BNIs are profiled by introducing the brief history of neuromorphics, reviewing the recent progresses on related areas, and discussing the future advances and challenges that lie ahead.

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer.

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10-6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm-2 eV-1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77-227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

Interface Chemistry and Dielectric Optimization of TMA-Passivated high-k/Ge Gate Stacks by ALD-Driven Laminated Interlayers.

In the present study, a comparative study on the influence of different laminated stacks driven by aomic layer deposition (ALD) on the interfacial and electrcial properties of high-k/Ge gate stacks passivated by trimethylaluminum (TMA) has been performed in detail via X-ray photoelectron spectroscopy (XPS) and electrical measurements. XPS measurements indicate that HfO2/Al2O3/Ge gate stacks can effectively inhibit the formation of Ge suboxides and a low-k germanate layer. Compared to Al2O3/HfO2 and HfO2/Al2O3/HfO2 gate stacks, the HfO2/Al2O3/Ge metal oxide semiconductor (MOS) capacitors exhibited improved electrical performance, including a maximum permittivity of 18.15, disappearing hysteresis, an almost neglected flat band voltage of 0.01 V, and a minimum leakage current density of 3.82 × 10-8 A/cm2 at room temperature. Especially, the leakage current mechanisms of Ge-MOS capacitors based on different laminated stacks measured at room temperature and low temperature (77-327 K) have been comprehensively analyzed. By comparing three different laminated gate stacks, it can be inferred that HfO2/Al2O3/Ge gate stacks have a potential application prospect in Ge-based microelectronic devices.