Traceability of Sustainability and Safety in Fishery Supply Chain Management Systems Using Radio Frequency Identification Technology.

At present, sustainability and emerging technology are the main issues in any supply chain management (SCM) sector. At the same time, the ongoing pandemic is increasing consumers' concerns about food safety, processing, and distribution, which should meet sustainability requirements. Thus, supervision and monitoring of product quality with symmetric information traceability are important in fresh food and fishery SCM. Food safety and traceability systems based on blockchain, Internet of Things (IoT), wireless sensor networks (WSN), and radio frequency identification (RFID) provide reliability from production to consumption. This review focuses on RFID-based traceability systems in fisheries' SCM, which have been employed globally to ensure fish quality and security, and summarizes their advantages in real-time applications. The results of this study will help future researchers to improve consumers' trust in fisheries SCM. Thus, this review aims to provide guidelines and solutions for enhancing the reliability of RFID-based traceability in food SCM systems so to ensure the integrity and transparency of product information.

Assessment of health risks and individuals' willingness to participate in drinking water management at flood-prone Pahang River Basin, Malaysia.

Rivers, the main source of the domestic water supply in Malaysia, have been threatened by frequent flooding in recent years. This study aims to assess human health risks associated with exposure to concentrated heavy metals in a flood-prone region of Malaysia and investigate the affected individuals' willingness to participate in managing water resources. Hazard indices and cancer risks associated with water contamination by heavy metals have been assessed following the method prescribed by the US Environmental Protection Agency. Yearly data of heavy metal contamination (Cd, Cr, Pb, Zn, Fe), water quality parameters (DO, BOD, COD, pH), and climatic information (annual rainfall, annual temperature) have been collected from the Department of Environment and Meteorological Department of Malaysia, respectively. The inductively coupled plasma mass spectrometry technique has been used by the department of environment for analyzing heavy metal concentration in river water samples. In this study, data from a stratified random sample of households in the affected region were analyzed, using partial least squares structural equation modeling, to predict the link between individuals' perceptions and attitudes about water resources and their willingness to engage in water management program. The health risk estimation indicated that the hazard index values were below the acceptable limit, representing no non-carcinogenic risk to adults and children residing in the study area via oral intake and dermal adsorption of water. However, the calculated value for cancer risk signified possible carcinogenic risks associated with Pb and Cd. In general, contamination due to pollution and flooding tends to increase in the basin region, and appropriate management is needed. The results identified perceived water quality as a significant factor influencing people's attitudes toward involvement in water management programs. As in many developing countries, there is no legal provision guaranteeing public representation in water management in Malaysia. The conclusion discusses the importance of these for the literature and for informing future policy actions.

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM.

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID-EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 µW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 µW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

A high-speed and low-offset dynamic latch comparator.

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 µm CMOS process show that the equivalent input-referred offset voltage is 720 µV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 µW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 µm × 59.70 µm.

Designing a ring-VCO for RFID transponders in 0.18 µm CMOS process.

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 µm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

High-speed current dq PI controller for vector controlled PMSM drive.

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.