Advances in the fabrication of graphene transistors on flexible substrates.

Graphene is an ideal candidate for next generation applications as a transparent electrode for electronics on plastic due to its flexibility and the conservation of electrical properties upon deformation. More importantly, its field-effect tunable carrier density, high mobility and saturation velocity make it an appealing choice as a channel material for field-effect transistors (FETs) for several potential applications. As an example, properly designed and scaled graphene FETs (Gr-FETs) can be used for flexible high frequency (RF) electronics or for high sensitivity chemical sensors. Miniaturized and flexible Gr-FET sensors would be highly advantageous for current sensors technology for in vivo and in situ applications. In this paper, we report a wafer-scale processing strategy to fabricate arrays of back-gated Gr-FETs on poly(ethylene naphthalate) (PEN) substrates. These devices present a large-area graphene channel fully exposed to the external environment, in order to be suitable for sensing applications, and the channel conductivity is efficiently modulated by a buried gate contact under a thin Al2O3 insulating film. In order to be compatible with the use of the PEN substrate, optimized deposition conditions of the Al2O3 film by plasma-enhanced atomic layer deposition (PE-ALD) at a low temperature (100 °C) have been developed without any relevant degradation of the final dielectric performance.

Interface Electrical Properties of Al2O3 Thin Films on Graphene Obtained by Atomic Layer Deposition with an in Situ Seedlike Layer.

High-quality thin insulating films on graphene (Gr) are essential for field-effect transistors (FETs) and other electronics applications of this material. Atomic layer deposition (ALD) is the method of choice to deposit high-κ dielectrics with excellent thickness uniformity and conformal coverage. However, to start the growth on the sp2 Gr surface, a chemical prefunctionalization or the physical deposition of a seed layer are required, which can effect, to some extent, the electrical properties of Gr. In this paper, we report a detailed morphological, structural, and electrical investigation of Al2O3 thin films grown by a two-steps ALD process on a large area Gr membrane residing on an Al2O3-Si substrate. This process consists of the H2O-activated deposition of a Al2O3 seed layer a few nanometers in thickness, performed in situ at 100 °C, followed by ALD thermal growth of Al2O3 at 250 °C. The optimization of the low-temperature seed layer allowed us to obtain a uniform, conformal, and pinhole-free Al2O3 film on Gr by the second ALD step. Nanoscale-resolution mapping of the current through the dielectric by conductive atomic force microscopy (CAFM) demonstrated an excellent laterally uniformity of the film. Raman spectroscopy measurements indicated that the ALD process does not introduce defects in Gr, whereas it produces a partial compensation of Gr unintentional p-type doping, as confirmed by the increase of Gr sheet resistance (from ∼300 Ω/sq in pristine Gr to ∼1100 Ω/sq after Al2O3 deposition). Analysis of the transfer characteristics of Gr field-effect transistors (GFETs) allowed us to evaluate the relative dielectric permittivity (ε = 7.45) and the breakdown electric field (EBD = 7.4 MV/cm) of the Al2O3 film as well as the transconductance and the holes field-effect mobility (∼1200 cm2 V-1 s-1). A special focus has been given to the electrical characterization of the Al2O3-Gr interface by the analysis of high frequency capacitance-voltage measurements, which allowed us to elucidate the charge trapping and detrapping phenomena due to near-interface and interface oxide traps.

Micro- and nanoscale electrical characterization of large-area graphene transferred to functional substrates.

Chemical vapour deposition (CVD) on catalytic metals is one of main approaches for high-quality graphene growth over large areas. However, a subsequent transfer step to an insulating substrate is required in order to use the graphene for electronic applications. This step can severely affect both the structural integrity and the electronic properties of the graphene membrane. In this paper, we investigated the morphological and electrical properties of CVD graphene transferred onto SiO2 and on a polymeric substrate (poly(ethylene-2,6-naphthalene dicarboxylate), briefly PEN), suitable for microelectronics and flexible electronics applications, respectively. The electrical properties (sheet resistance, mobility, carrier density) of the transferred graphene as well as the specific contact resistance of metal contacts onto graphene were investigated by using properly designed test patterns. While a sheet resistance R sh ≈ 1.7 kΩ/sq and a specific contact resistance ρc ≈ 15 kΩ·µm have been measured for graphene transferred onto SiO2, about 2.3× higher R sh and about 8× higher ρc values were obtained for graphene on PEN. High-resolution current mapping by torsion resonant conductive atomic force microscopy (TRCAFM) provided an insight into the nanoscale mechanisms responsible for the very high ρc in the case of graphene on PEN, showing a ca. 10× smaller "effective" area for current injection than in the case of graphene on SiO2.