Miniaturizing Transmon Qubits Using van der Waals Materials.

Quantum computers can potentially achieve an exponential speedup versus classical computers on certain computational tasks, recently demonstrated in superconducting qubit processors. However, the capacitor electrodes that comprise these qubits must be large in order to avoid lossy dielectrics. This tactic hinders scaling by increasing parasitic coupling among circuit components, degrading individual qubit addressability, and limiting the spatial density of qubits. Here, we take advantage of the unique properties of van der Waals (vdW) materials to reduce the qubit area by >1000 times while preserving the capacitance while maintaining quantum coherence. Our qubits combine conventional aluminum-based Josephson junctions with parallel-plate capacitors composed of crystalline layers of superconducting niobium diselenide and insulating hexagonal boron nitride. We measure a vdW transmon T1 relaxation time of 1.06 µs, demonstrating a path to achieve high-qubit-density quantum processors with long coherence times, and the broad utility of layered heterostructures in low-loss, high-coherence quantum devices.

Symmetry-aware reservoir computing.

We demonstrate that matching the symmetry properties of a reservoir computer (RC) to the data being processed dramatically increases its processing power. We apply our method to the parity task, a challenging benchmark problem that highlights inversion and permutation symmetries, and to a chaotic system inference task that presents an inversion symmetry rule. For the parity task, our symmetry-aware RC obtains zero error using an exponentially reduced neural network and training data, greatly speeding up the time to result and outperforming artificial neural networks. When both symmetries are respected, we find that the network size N necessary to obtain zero error for 50 different RC instances scales linearly with the parity-order n. Moreover, some symmetry-aware RC instances perform a zero error classification with only N=1 for n≤7. Furthermore, we show that a symmetry-aware RC only needs a training data set with size on the order of (n+n/2) to obtain such a performance, an exponential reduction in comparison to a regular RC which requires a training data set with size on the order of n2^{n} to contain all 2^{n} possible n-bit-long sequences. For the inference task, we show that a symmetry-aware RC presents a normalized root-mean-square error three orders-of-magnitude smaller than regular RCs. For both tasks, our RC approach respects the symmetries by adjusting only the input and the output layers, and not by problem-based modifications to the neural network. We anticipate that the generalizations of our procedure can be applied in information processing for problems with known symmetries.

Making high-quality quantum microwave devices with van der Waals superconductors.

Ultra low-loss microwave materials are crucial for enhancing quantum coherence and scalability of superconducting qubits. Van der Waals (vdW) heterostructure is an attractive platform for quantum devices due to the single-crystal structure of the constituent two-dimensional (2D) layered materials and the lack of dangling bonds at their atomically sharp interfaces. However, new fabrication and characterization techniques are required to determine whether these structures can achieve low loss in the microwave regime. Here we report the fabrication of superconducting microwave resonators using NbSe2that achieve a quality factorQ> 105. This value sets an upper bound that corresponds to a resistance of⩽192µΩwhen considering the additional loss introduced by integrating NbSe2into a standard transmon circuit. This work demonstrates the compatibility of 2D layered materials with high-quality microwave quantum devices.

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices.

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10-6, and a 4 × 4 array can be fully addressed with bit select error rates of 10-6. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.