Depletion Mode MOSFET Using La-Doped BaSnO3 as a Channel Material.

The high room-temperature mobility that can be achieved in BaSnO3 has created significant excitement for its use as channel material in all-perovskite-based transistor devices such as ferroelectric field effect transistor (FET). Here, we report on the first demonstration of n-type depletion-mode FET using hybrid molecular beam epitaxy grown La-doped BaSnO3 as a channel material. The devices utilize a heterostructure metal-oxide semiconductor FET (MOSFET) design that includes an epitaxial SrTiO3 barrier layer capped with a thin layer of HfO2 used as a gate dielectric. A field-effect mobility of ∼70 cm2 V-1 s-1, a record high transconductance value of >2mS/mm at room temperature, and the on/off ratio exceeding 107 at 77 K were obtained. Using temperature- and frequency-dependent transport measurements, we quantify the impact of the conduction band offset at the BaSnO3/SrTiO3 interface as well as bulk and interface traps on device characteristics.

Cyclical Thinning of Black Phosphorus with High Spatial Resolution for Heterostructure Devices.

A high spatial resolution, cyclical thinning method for realizing black phosphorus (BP) heterostructures is reported. This process utilizes a cyclic technique involving BP surface oxidation and vacuum annealing to create BP flakes as thin as 1.6 nm. The process also utilizes a spatially patternable mask created by evaporating Al that oxidizes to form Al2O3, which stabilizes the unetched BP regions and enables the formation of lateral heterostructures with spatial resolution as small as 150 nm. This thinning/patterning technique has also been used to create the first-ever lateral heterostructure BP metal oxide semiconductor field-effect transistor (MOSFET), in which half of a BP flake was thinned in order to increase its band gap. This heterostructure MOSFET showed an ON/OFF current ratio improvement of 1000× compared to homojunction MOSFETs.

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents.

Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/µm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/µm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.