Análisis de las Variaciones Anatómicas y Dimensionales del Canal Nasopalatino Mediante Tomografía Computarizada de Haz Cónico / Analysis of the Anatomical and Dimensional Variations of the Nasopalatine Canal by Cone Beam Computed Tomography

El conocimiento anatómico del canal nasopalatino (CNP) es fundamental para la realización de cirugías en el sector anterior del maxilar y así prever posibles complicaciones. El objetivo de este trabajo es evaluar y determinar las variaciones anatómicas y dimensionales del CNP según sexo, edad y estado dental. Este estudio transversal analizó un total de 251 imágenes de TCHC obtenidas de la base de datos del Servicio de Imagenología Oral y Maxilofacial de la Facultad de Odontología de la Universidad Andrés Bello, Viña del Mar, Chile. Para evaluar la asociación estadística entre variaciones del CNP con sexo, edad y estado dentario se realizó la prueba T de Student, chi-cuadrado y ANOVA (p0,05). Además, se detectó diferencia significativa entre el estado dentario y la dimensión de la tabla vestibular en relación con el CNP (p<0,01). Se deben considerar las variaciones de CNP para evitar posibles complicaciones durante los procedimientos quirúrgicos.

SUMMARY: Anatomical knowledge of the nasopalatine canal (PNC) is essential for performing surgeries in the anterior sector of the maxilla and thus anticipating possible complications. The objective of this work is to evaluate and determine the anatomical and dimensional variations of the CNP according to sex, age and dental status. This cross-sectional study analyzed a total of 251 CBCT images obtained from the database of the Oral and Maxillofacial Imaging Service of the Faculty of Dentistry of the Andrés Bello University, Viña del Mar, Chile. To evaluate the statistical association between CNP variations with sex, age and dental status, the Student's T test, chi-square and ANOVA (p0.05). In addition, a significant difference was detected between the dental state and the dimension of the vestibular table in relation to the CNP (p<0.01). CNP variations should be considered to avoid potential complications during surgical procedures.

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices.

The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.

Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems.

Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices.

VLSI Design of Trusted Virtual Sensors.

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 µ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).