Loss of short-latency afferent inhibition and emergence of afferent facilitation following neuromuscular electrical stimulation.

Neuromuscular electrical stimulation (NMES) increases the excitability of corticospinal (CS) pathways by altering circuits in motor cortex (M1). How NMES affects circuits interposed between the ascending afferent volley and descending CS pathways is not known. Presently, we hypothesized that short-latency afferent inhibition (SAI) would be reduced and afferent facilitation (AF) enhanced when NMES increased CS excitability. NMES was delivered for 40 min over the ulnar nerve. To assess CS excitability, motor evoked potentials (MEPs) were evoked using transcranial magnetic stimulation (TMS) delivered at 120% resting threshold for first dorsal interosseus muscle. These MEPs increased by ∼1.7-fold following NMES, demonstrating enhanced CS excitability. SAI and AF were tested by delivering a "conditioning" electrical stimulus to the ulnar nerve 18-25 ms and 28-35 ms before a "test" TMS pulse, respectively. Conditioned MEPs were compared to unconditioned MEPs evoked in the same trials. TMS was adjusted so unconditioned MEPs were not different before and after NMES. At the SAI interval, conditioned MEPs were 25% smaller than unconditioned MEPs before NMES but conditioned and unconditioned MEPs were not different following NMES. At the AF interval, conditioned MEPs were not different from unconditioned MEPs before NMES, but were facilitated by 33% following NMES. Thus, when NMES increases CS excitability there are concurrent changes in the effect of afferent input on M1 excitability, resulting in a net increase in the excitatory effect of the ascending afferent volley on CS circuits. Maximising this excitatory effect on M1 circuits may help strengthen CS pathways and improve functional outcomes of NMES-based rehabilitation programs.

"Metallic" and "insulating" behavior of the two-dimensional electron gas on a vicinal surface of Si MOSFET'S.

The resistance R of the 2DEG on the vicinal Si surface shows unusual behavior which is very different from that in Si (100) MOSFET's studied earlier. The low-temperature crossover from dR/dT<0 ("insulator") to dR/dT>0 ("metal") occurs at a low resistance of R(c)square approximately 0.04xh/e2. This crossover, which we attribute to the existence of a narrow impurity band at the interface, is accompanied by a distinct hysteresis in the resistance. At higher temperatures, another change in the sign of dR/dT is seen. We describe it by temperature dependent impurity scattering of the 2DEG near the transition from the degenerate to nondegenerate state.