Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection.

Food contamination by aflatoxins is an urgent global issue due to its high level of toxicity and the difficulties in limiting the diffusion. Unfortunately, current detection techniques, which mainly use biosensing, prevent the pervasive monitoring of aflatoxins throughout the agri-food chain. In this work, we investigate, through ab initio atomistic calculations, a pyrrole-based Molecular Field Effect Transistor (MolFET) as a single-molecule sensor for the amperometric detection of aflatoxins. In particular, we theoretically explain the gate-tuned current modulation from a chemical-physical perspective, and we support our insights through simulations. In addition, this work demonstrates that, for the case under consideration, the use of a suitable gate voltage permits a considerable enhancement in the sensor performance. The gating effect raises the current modulation due to aflatoxin from 100% to more than 103÷104%. In particular, the current is diminished by two orders of magnitude from the µA range to the nA range due to the presence of aflatoxin B1. Our work motivates future research efforts in miniaturized FET electrical detection for future pervasive electrical measurement of aflatoxins.

VirtLAB: A Low-Cost Platform for Electronics Lab Experiments.

The recent SARS-CoV2 pandemic has put a great challenge on university courses. Electronics teaching requires real laboratory experiences for students, which cannot be realized if access to physical infrastructures is prohibited. A possible solution would be to distribute to students, at home, electronics equipment suitable for laboratory experiments, but no reasonable product is currently available off-the-shelf. In this paper, the design and development of a very-low-cost experimental board tailored to these needs is presented. It contains both programmable prototyping circuitry based on a microcontroller and an FPGA and a set of measurement instruments, similar to the ones found on a typical lab desk, such as a digital storage oscilloscope, multimeter, analog signal generator, logic state analyzer and digital pattern generator. A first board, suitable for analog and digital electronics experiments, has been designed and manufactured, and is described in this paper. The board has been successfully used in master's degrees and PhD courses.

Nanomaterials to Fight Cancer: An Overview on Their Multifunctional Exploitability.

In recent years the worldwide research community has highlighted innumerable benefits of nanomaterials in cancer detection and therapy. Nevertheless, the development of cancer nanomedicines and other bionanotechnology requires a huge amount of considerations about the interactions of nanomaterials and biological systems, since long-term effects are not yet fully known. Open issues remain the determination of the nanoparticles distributions patterns and the internalization rate into the tumor while avoiding their accumulation in internal organs or other healthy tissues. The purpose of this work is to provide a standard overview of the most recent advances in nanomaterials to fight cancer and to collect trends and future directions to follow according to some critical aspects still present in this field. Complementary to the very recent review of Wolfram and Ferrari which discusses and classifies successful clinically-approved cancer nanodrugs as well as promising candidates in the pipeline, this work embraces part of their proposed classification system based on the exploitation of multifunctionality and extends the review to peer-reviewed journal articles published in the last 3 years identified through international databases.

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis.

In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC.

Data Processing and Information Classification-An In-Memory Approach.

To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that can elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such a system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose a hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.