A facile thermal-treatment route to synthesize ZnO nanosheets and effect of calcination temperature.

A facile thermal-treatment route was successfully used to synthesize ZnO nanosheets. Morphological, structural, and optical properties of obtained nanoparticles at different calcination temperatures were studied using various techniques. The FTIR, XRD, EDX, SEM and TEM images confirmed the formation of ZnO nanosheets through calcination in the temperature between 500 to 650 °C. The SEM images showed a morphological structure of ZnO nanosheets, which inclined to crumble at higher calcination temperatures. The XRD and FTIR spectra revealed that the samples were amorphous at 30 °C but transformed into a crystalline structure during calcination process. The average particle size and degree of crystallinity increased with increasing calcination temperature. The estimated average particle sizes from TEM images were about 23 and 38 nm for the lowest and highest calcination temperature i.e. 500 and 650 °C, respectively. The optical properties were determined by UV-Vis reflection spectrophotometer and showed a decrease in the band gap with increasing calcination temperature.

Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography.

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, 'on/off' ratio, and threshold voltage were observed. The devices are 'on' state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.