Impact of electrode geometry and thickness on planar on-chip microsupercapacitors.

We report an assessment of the influence of both finger geometry and vertically-oriented carbon nanofiber lengths in planar micro-supercapacitors. Increasing the finger number leads to an up-scaling in areal power densities, which increases with scan rate. Growing the nanofibers longer, however, does not lead to a proportional growth in capacitance, proposedly related to limited ion penetration of the electrode.

Low temperature and cost-effective growth of vertically aligned carbon nanofibers using spin-coated polymer-stabilized palladium nanocatalysts.

We describe a fast and cost-effective process for the growth of carbon nanofibers (CNFs) at a temperature compatible with complementary metal oxide semiconductor technology, using highly stable polymer-Pd nanohybrid colloidal solutions of palladium catalyst nanoparticles (NPs). Two polymer-Pd nanohybrids, namely poly(lauryl methacrylate)-block-poly((2-acetoacetoxy)ethyl methacrylate)/Pd (LauMA x -b-AEMA y /Pd) and polyvinylpyrrolidone/Pd were prepared in organic solvents and spin-coated onto silicon substrates. Subsequently, vertically aligned CNFs were grown on these NPs by plasma enhanced chemical vapor deposition at different temperatures. The electrical properties of the grown CNFs were evaluated using an electrochemical method, commonly used for the characterization of supercapacitors. The results show that the polymer-Pd nanohybrid solutions offer the optimum size range of palladium catalyst NPs enabling the growth of CNFs at temperatures as low as 350 °C. Furthermore, the CNFs grown at such a low temperature are vertically aligned similar to the CNFs grown at 550 °C. Finally the capacitive behavior of these CNFs was similar to that of the CNFs grown at high temperature assuring the same electrical properties thus enabling their usage in different applications such as on-chip capacitors, interconnects, thermal heat sink and energy storage solutions.

Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices.

We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.