ABSTRACT
A facile fabrication of a hetero-sized nanocluster array has been demonstrated by using inert-gas condensation at room temperature. The array consisted of 1.5 and 3.2 nm sized gold clusters. The nonvolatile memory characteristics of a memory cell that had a hetero-sized nanocluster array to be used as a charge-trapping layer were compared to those of two cells that had 1.5 and 3.2 nm sized cluster arrays, respectively. While the average cluster size or the average number of electrons trapped in a cluster was reflected in the programming/erasing characteristics, the nanostructure effect was revealed in the retention characteristics, i.e. the proposed cell was found to have the gentlest degradation of the memory window. This can be explained by a preferential pathway for charge-carrier redistribution, caused by the ionization potential difference between the two nanoclusters of different sizes.
ABSTRACT
Metal nanoclusters were fabricated by inert-gas condensation in a sputtering reactor. From transmission electron microscopy, it was confirmed that copper nanoclusters with a high degree of monodispersity in size of about 5 nm were successfully produced. The conductance of the percolated nanocluster film was measured. In order to incorporate nano-scale arrangement characterizations in nano-devices being operated in air, aging experiments of the specimen after long time in air were carried. Negative temperature coefficient of resistance suggests that surface native copper oxide in core-shell structured nanoclusters was mainly responsible for the conductance, because copper oxide is known as semiconductor. After aged at higher than 100 degrees C, the conductance at room temperature didn't return to the original value. This irreversible phenomenon might be due to coarsening and/or coalescence of copper nanoclusters.
ABSTRACT
We have fabricated Si(1-x)Ge(x) alloy nanowire devices with Ni and Ni/Au electrodes. The electrical transport characteristics of the alloy nanowires depended strongly on the annealing temperature and contact metals. Ni/Au-contacted devices annealed at 400 degrees C showed p-type transistor behavior as well as a resistance switching effect, while no switching was observed from Ni-contacted alloy nanowire devices. To identify the origin of such a hysteretic resistance switching effect, we constructed nanowire devices on a 40 nm Si(3)N(4) membrane. Transmission electron microscopy analysis combined with electrical transport measurements revealed that devices contacted with Ni/Au, and thereby showing resistance switching, have Au atoms right next to the alloy nanowire.
