Synaptic Segmented Transistor with Improved Linearity by Schottky Junctions and Accelerated Speed by Double-Layered Nitride.

Neuromorphic devices have been extensively studied to overcome the limitations of a von Neumann system for artificial intelligence. A synaptic device is one of the most important components in the hardware integration for a neuromorphic system because a number of synaptic devices can be connected to a neuron with compactness as high as possible. Therefore, synaptic devices using silicon-based memory, which are advantageous for a high packing density and mass production due to matured fabrication technologies, have attracted considerable attention. In this study, a segmented transistor devoted to an artificial synapse is proposed for the first time to improve the linearity of the potentiation and depression (P/D). It is a complementary metal oxide semiconductor (CMOS)-compatible device that harnesses both non-ohmic Schottky junctions of the source and drain for improved weight linearity and double-layered nitride for enhanced speed. It shows three distinct and unique segments in drain current-gate voltage transfer characteristics induced by Schottky junctions. In addition, the different stoichiometries of SixNy for a double-layered nitride is utilized as a charge trap layer for boosting the operation speed. This work can bring the industry potentially one step closer to realizing the mass production of hardware-based synaptic devices in the future.

Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs.

A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

Nano-electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments.

A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of the NEM-switch-based PUF is its use of stiction. Stiction is one of the chronic problems associated with micro- and nano-electromechanical system (MEMS/NEMS) devices; however, here, it was utilized to intentionally implement a PUF for hardware-based security. The stiction is caused by capillary and van der Waals forces, producing strong adhesion, which can be utilized to design a highly robust and stable PUF. The probability that stiction will occur on either of two gates in the NEM switch is the same, and consequently, the occurrence of the stiction is random and unique, which is critical to its PUF performance. This uniqueness was evaluated by measuring the interchip Hamming distance (interchip HD), which characterizes how different responses are made when the same challenge is applied. Uniformity was also evaluated by the proportion of "1" or "0" in the response bit-string. The reliability of the proposed PUF device was assessed by stress tests under harsh environments such as high temperature, high dose radiation, and microwaves.

Realization of efficient semitransparent organic photovoltaic cells with metallic top electrodes: utilizing the tunable absorption asymmetry.

Efficient semitransparent organic photovoltaic (OPV) cells are presented in an inverted geometry employing ZnS/ Ag/ WO3 (ZAW) as a top anode and ITO/ Cs2CO3 as a bottom cathode. Upon identification of the light absorption that differs depending on the illumination direction, the degree of the absorption asymmetry is tuned by varying the ZAW structure to maximize the efficiency for one direction or to balance it for both directions. Power conversion efficiency close to that of conventional opaque OPV cells is demonstrated in semitransparent cells for the ITO side illumination by taking advantage of the internal reflection occurring at the organic/ZAW interface. Cells with efficiencies that are reduced but balanced for both illumination directions are also demonstrated.