Fumed Silica-Based Ultra-High-Purity Synthetic Quartz Powder via Sol-Gel Process for Advanced Semiconductor Process beyond Design Rule of 3 nm.

Fumed silica-based ultra-high-purity synthetic quartz powder was developed via the sol-gel process to apply to quartz wares and quartz crucibles for use in advanced semiconductor processes. The process conditions of preparing potassium silicate solution, gelation, and cleaning were optimized, i.e., the relative ratio of fumed silica (10 wt%) to KOH (4 wt%) for potassium silicate solution, gelation time 3 h, and cleaning for 1 h with 5 wt% HCl solution. It was observed that the gelation time strongly affected the size distribution of the quartz powder; i.e., a longer gelation time led to a larger size (d50) of the synthesized quartz powder: 157 µm for 2 h and 331 µm for 5 h. In particular, it was found that the morphology of the as-synthesized quartz powder greatly depended on the pulverizing process; i.e., the shape of quartz powder was shown to be rod-shaped for the without-gel-pulverizing process and granular-shaped with the process. We expect that the fumed silica-based ultra-high-purity quartz powder with an impurity level of 74.1 ppb synthesized via the sol-gel process is applicable as a raw material for quartz wares and crucibles for advanced semiconductor processes beyond the design rule of 3 nm.

Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3 Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array.

The learning and inference efficiencies of an artificial neural network represented by a cross-point synaptic memristor array can be achieved using a selector, with high selectivity (Ion /Ioff ) and sufficient death region, stacked vertically on a synaptic memristor. This can prevent a sneak current in the memristor array. A selector with multiple jar-shaped conductive Cu filaments in the resistive switching layer is precisely fabricated by designing the Cu ion concentration depth profile of the CuGeSe layer as a filament source, TiN diffusion barrier layer, and Ge3 Se7 switching layer. The selector performs super-linear-threshold-switching with a selectivity of > 107 , death region of -0.70-0.65 V, holding time of 300 ns, switching speed of 25 ns, and endurance cycle of > 106 . In addition, the mechanism of switching is proven by the formation of conductive Cu filaments between the CuGeSe and Ge3 Se7 layers under a positive bias on the top Pt electrode and an automatic rupture of the filaments after the holding time. Particularly, a spiking deep neural network using the designed one-selector-one-memory cross-point array improves the Modified National Institute of Standards and Technology classification accuracy by ≈3.8% by eliminating the sneak current in the cross-point array during the inference process.

Design of n+-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector.

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (I on /I off ) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a [Formula: see text] bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Dislocation sink annihilating threading dislocations in strain-relaxed Si1-x Ge x layer.

We proposed a dislocation sink technology for achieving Si1-x Ge x multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si1-x Ge x channel. A generation of a dislocation sink via H+ implantations in a strain-relaxed Si0.7Ge0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si0.7Ge0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [SiI or GeI + V Si or V Ge â†’ Si1-x Ge x ] annihilation process, where SiI, GeI, V Si, and V Ge are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H+ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 1015 atoms cm-2 and 800 °C.

Double Pinned Perpendicular-Magnetic-Tunnel-Junction Spin-Valve Providing Multi-level Resistance States.

A new design for high density integration greater than gigabits of perpendicular-magnetic-tunnel-junction (p-MTJ) spin-valve, called the double pinned (i.e., bottom and top pinned structures) p-MTJ spin-valve achieved a multi-level memory-cell operation exhibiting four-level resistances. Three key magnetic properties, the anisotropy exchange field (Hex) of the bottom pinned structure, the coercivity (Hc) of the double free-layer, and the Hc of the top pinned structure mainly determined four-level resistances producing tunneling-magnetoresistance (TMR) ratios of 152.6%, 33.6%, and 166.5%. The three key-design concepts are: i) the bottom pinned structure with a sufficiently large Hex to avoid a write-error, ii) the Hc of the double free-layer (i.e., ~0.1 kOe) much less than the Hc of the top pinned structure (i.e., ~1.0 kOe), and iii) the top pinned structure providing different electron spin directions.

Performance of thyristor memory device formed by a wet etching process.

Thyristor random access memory without a capacitor has been highlighted for its significant potential to replace current dynamic random access memory. We fabricated a two-terminal (2-T) thyristor by wet chemical etching techniques on n+-p-n-p+ silicon epitaxial layers, which have the proper thicknesses and carrier concentrations, as provided by technology computer-aided design simulation. The etched features such as etch rate, surface roughness, and morphologies, in a potassium hydroxide (KOH) and an isotropic etchant, were compared. The type of silicon etchant strongly affected the etched shapes of the side wall and therefore critically influenced the device performance with varying turn-on voltages. The turn-on voltage of thyristor fabricated with a KOH solution showed a consistent tendency of operation voltage in the range of 2.2-2.5 V regardless of the cell size, while the thyristor formulated with isotropic etchant had an operation voltage which increased from about 2.3-4.4 V as the device dimension decreased from 200 µm to 10 µm. The optimized 2-T thyristor showed a memory window of about 2 V, a nearly zero-subthreshold swing, and a current on-off ratio of about 104-105.

Tunneling-Magnetoresistance Ratio Comparison of MgO-Based Perpendicular-Magnetic-Tunneling-Junction Spin Valve Between Top and Bottom Co2Fe6B2 Free Layer Structure.

For the perpendicular-magnetic-tunneling-junction (p-MTJ) spin valve with a nanoscale-thick bottom Co2Fe6B2 free layer ex situ annealed at 400 °C, which has been used as a common p-MTJ structure, the Pt atoms of the Pt buffer layer diffused into the MgO tunneling barrier. This transformed the MgO tunneling barrier from a body-centered cubic (b.c.c) crystallized layer into a mixture of b.c.c, face-centered cubic, and amorphous layers and rapidly decreased the tunneling-magnetoresistance (TMR) ratio. The p-MTJ spin valve with a nanoscale-thick top Co2Fe6B2 free layer could prevent the Pt atoms diffusing into the MgO tunneling barrier during ex situ annealing at 400 °C because of non-necessity of a Pt buffer layer, demonstrating the TMR ratio of ~143 %.

Effect of coupling ability between a synthetic antiferromagnetic layer and pinned layer on a bridging layer of Ta, Ti, and Pt in perpendicular-magnetic tunnel junctions.

By fabricating CoFeB/MgO/CoFeB-based perpendicular-magnetic tunnel junction (p-MTJ) spin-valves stacked with a [Co/Pd] n -SyAF layer based on a TiN bottom electrode on a 12 inch Si wafer (001) substrate, we investigated how the bridging layers of Ta, Ti, and Pt and their thickness variation affected the tunneling magneto-resistance (TMR) ratio of Co2Fe6B2 pinned-layer behavior in magnetic-tunnel-junctions. TMR ratios for Ta, Ti, and Pt bridging layers were observed to be 64.1, 70.2, and 29.5%, respectively. It was confirmed by high resolution transmission electron microscopy (HR-TEM) that this difference resulted from CoFeB/MgO/CoFeB MTJ layers with Ta and Ti bridging layers being textured well with a bcc (100) structure, indicating that Ta and Ti bridging layers bridged SyAF fcc (111) and MTJ bcc (100). On the other hand, the MTJ layer with Pt bridging layer was incorrectly textured, indicating that a Pt bridging layer is unsuitable to bridge SyAF fcc (111) and MTJ bcc (100) due to Pt being diffused into the CoFeB pinned-layer. In addition, perpendicular magnetic anisotropy (PMA) behavior of the CoFeB pinned-layer was found to depend strongly on a bridging layer thickness; higher TMRs of Ta and Ti were observed at the optimal bridging layers' thickness, which enable the realization of PMAs of the pinned-layer and ferro-coupling of the pinned-layer with the lower-SyAF layer. Among the three bridging materials (Ta, Ti, and Pt), we observed that Ti showed the highest TMR ratio and widest thickness range for a high TMR ratio, indicating that a higher TMR ratio is needed to obtain the best deposition process margin.

Co2Fe6B2/MgO-based perpendicular spin-transfer-torque magnetic-tunnel-junction spin-valve without [Co/Pt] n lower synthetic-antiferromagnetic layer.

We design a Co2Fe6B2/MgO-based p-MTJ spin-valve without a [Co/Pt] n lower synthetic-antiferromagnetic (SyAF) layer to greatly reduce the 12-inch wafer fabrication cost of the p-MTJ spin-valve. This spin-valve achieve a tunneling magnetoresistance (TMR) of 158% and an exchange field (H ex) of 1.4 kOe at an ex situ annealing temperature of >350 °C, which ensures writing error immunity. In particular, the TMR ratio strongly depends on the body-center-cubic capping-layer nanoscale thickness (t bcc), i.e., the TMR ratio peaks at t bcc = 0.6 nm.

Influence of face-centered-cubic texturing of Co2Fe6B2 pinned layer on tunneling magnetoresistance ratio decrease in Co2Fe6B2/MgO-based p-MTJ spin valves stacked with a [Co/Pd](n)-SyAF layer.

The TMR ratio of Co2Fe6B2/MgO-based p-MTJ spin valves stacked with a [Co/Pd]n-SyAF layer decreased rapidly when the ex situ magnetic annealing temperature (Tex) was increased from 275 to 325 °C, and this decrease was associated with degradation of the Co2Fe6B2 pinned layer rather than the Co2Fe6B2 free layer. At a Tex above 325 °C the amorphous Co2Fe6B2 pinned layer was transformed into a face-centered-cubic (fcc) crystalline layer textured from [Co/Pd]n-SyAF, abruptly reducing the Δ1 coherence tunneling of perpendicular-spin-torque electrons between the (100) MgO tunneling barrier and the fcc Co2Fe6B2 pinned layer.

The dependency of tunnel magnetoresistance ratio on nanoscale thicknesses of Co2Fe6B2 free and pinned layers for Co2Fe6B2/MgO-based perpendicular-magnetic-tunnel-junctions.

The tunnel magnetoresistance (TMR) ratio of a cobalt-iron-boron (CoFeB)-based perpendicular-magnetic-tunnel-junction (p-MTJ) spin valve is extremely sensitive to both nanoscale Co2Fe6B2 free- and pinned-layer thicknesses. The TMR ratio peaks at a Co2Fe6B2 free-layer thickness of 1.05 nm, while it peaks at a Co2Fe6B2 pinned-layer thickness of 1.59 nm, achieving 104%. The amount of tantalum diffused into the MgO tunneling barrier (originated from a tantalum seed) decreases with increasing Co2Fe6B2 free-layer thickness, while the amount of palladium diffused from a [Co/Pd]n SyAF layer decreases with increasing Co2Fe6B2 pinned-layer thickness, determining the crystallinity of the MgO tunneling barrier and the TMR ratio. In addition, the TMR ratio tended to decrease when the Co2Fe6B2 free layer and the Co2Fe6B2 pinned layer switched characteristics from interface-perpendicular anisotropic to in-plane anisotropic.

Etch characteristics of magnetic tunnel junction materials using bias pulsing in the CH4/N2O inductively coupled plasma.

The etch characteristics of magnetic tunneling junction (MTJ) related materials such as CoFeB, MgO, FePt, Ru, and W as hard mask have been investigated as functions of rf pulse biasing, substrate heating, and CH4/N2O gas combination in an inductively coupled plasma system. When CH4/N2O gas ratio was varied, at CH4/N2O gas ratio of 2:1, not only the highest etch rates but also the highest etch selectivity over W could be obtained. By increasing the substrate temperature, the linear increase of both the etch rates of MTJ materials and the etch selectivity over W could be obtained. The use of the rf pulse biasing improved the etch selectivity of the MTJ materials over hard mask such as W further. The surface roughness and residual thickness remaining on the etched surface of the CoFeB were also decreased by using rf pulse biasing and with the decrease of rf duty percentage. The improvement of etch characteristics by substrate heating and rf pulse biasing was possibly related to the formation of more stable and volatile etch compounds and the removal of chemically reacted compounds more easily on the etched CoFeB surface. Highly selective etching of MTJ materials over the hard mask could be obtained by using the rf pulse biasing of 30% of duty ratio and by increasing the substrate temperature to 200 degrees C in the CH4/N2O (2:1) plasmas.

Effect of RF pulsing biasing on the etching of magnetic tunnel junction materials using CH3OH.

The magnetic tunnel junction (MTJ)-related materials such as CoFeB, CoPt, MgO, and Ru, and W were etched using CH3OH in a pulse-biased inductively coupled plasma system and the effect of bias pulsing (100% 30% duty percentage) on the etch characteristics of the MTJ-related materials was investigated at the substrate temperature of 200 degrees C. The etch selectivity of MTJ-related materials over W was improved by using pulse-biasing possibly due to the formation of more stable and volatile etch products during the pulse-off time and the removal of the compounds more easily on the etched CoFeB surface during the pulse-on time. X-ray photoelectron spectroscopy also showed that the use of lower duty percentage decreases the residue thickness remaining on the etched MTJ materials indirectly indicated the higher volatility of the etch products by the bias pulsing. The etching of nano-patterned CoFeB masked with W also showed more anisotropic etch profile by pulse-biasing probably due to the increased the etch selectivity of CoFeB over W and the decreased redeposition of etch products on the sidewall of the CoFeB features. The most anisotropic CoFeB etch profiles could be observed by using CH3OH gas in the pulse biasing of 30% duty ratio.

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator.

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.

The effect of donor layer thickness on the power conversion efficiency of organic photovoltaic devices fabricated with a double small-molecular layer.

In organic photovoltaic (OPV) devices fabricated with a double small-molecular layer, the power conversion efficiency strongly depends on the thickness of the organic donor layer (here, copper phthalocyanine). In other words, the power conversion efficiency increases with the donor layer thickness up to a specific thickness ( approximately 12.7 nm) and then decreases beyond that thickness. This trend is associated with the light absorption and carrier transport resistance of the small-molecular donor layer, both of which strongly depend on the layer thickness. Experimental and calculated results showed that the short-circuit current due to light absorption increased with the donor layer thickness, while that due to current through the donor layer decreased with 1/R. Since the total short-circuit current is the product of the light absorption current and current through the donor layer, there is a trade-off, and the maximum power conversion efficiency occurs at a specific organic donor layer thickness (e.g. approximately 12.7 nm in this experiment).