Column Row Convolutional Neural Network: Reducing Parameters for Efficient Image Processing.

Recent advancements in deep learning have achieved significant progress by increasing the number of parameters in a given model. However, this comes at the cost of computing resources, prompting researchers to explore model compression techniques that reduce the number of parameters while maintaining or even improving performance. Convolutional neural networks (CNN) have been recognized as more efficient and effective than fully connected (FC) networks. We propose a column row convolutional neural network (CRCNN) in this letter that applies 1D convolution to image data, significantly reducing the number of learning parameters and operational steps. The CRCNN uses column and row local receptive fields to perform data abstraction, concatenating each direction's feature before connecting it to an FC layer. Experimental results demonstrate that the CRCNN maintains comparable accuracy while reducing the number of parameters and compared to prior work. Moreover, the CRCNN is employed for one-class anomaly detection, demonstrating its feasibility for various applications.

Grain-size adjustment in Hf0.5Zr0.5O2ferroelectric film to improve the switching time in Hf0.5Zr0.5O2-based ferroelectric capacitor.

By adjusting the rising time in annealing ferroelectric HfO2-based films, the grain size of the film can be controlled. In this study, we found that increasing the rising time from 10 to 30 s at an annealing temperature of 700 °C in N2atmosphere resulted in improved ferroelectric switching speed. This is because the larger grain size reduces the internal resistance components, such as the grain bulk resistance and grain boundary resistance, of the HZO film. This in turn lowers the overall equivalent resistance. By minimizing the RC time constants, increasing the grain size plays a key role in improving the polarization switching speed of ferroelectric films.

Experimental study of endurance characteristics of Al-doped HfO2ferroelectric capacitor.

In this work, the endurance characteristics of Al-doped HfO2(HAO)-based metal-ferroelectric-metal (MFM) capacitors (which were annealed at 1000 °C) with various doping concentrations were investigated. The doping concentration was optimized for the high annealing temperature (1000 °C) process. To investigate the impact of cycling pulses on the endurance characteristics of HAO-based MFM capacitor, the rise/fall time (tr/f) and hold time (th) for the cycling pulses were varied. Moreover, by adopting the recoverable fatigue process, the endurance characteristics under repetitive wake-up/fatigue processes were studied. The HAO capacitors achieved the remnant polarization (2Pr) of 23.767µC cm-2at pristine state under the high annealing temperature. Furthermore, it was demonstrated that the endurance characteristics (∼108cycles) of the HAO capacitors were comparable to them of other HfO2-based ferroelectric capacitors. Lastly but not least, it turned out that the amount of oxygen and oxygen vacancies in the HAO thin film was dependent of doping concentrations for the film. The impact of oxygen and oxygen vacancies was quantitatively analyzed, in detail, with TEM, XPS and GIXRD analysis.

Improved remnant polarization of Zr-doped HfO2 ferroelectric film by CF4/O2 plasma passivation.

In this work, the impact of fluorine (CF4) and oxygen (O2) plasma passivation on HfZrOx (HZO) based ferroelectric capacitor was investigated. By the fluorine passivation, the surface trap density and oxygen vacancies in the HZO-based Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors were suppressed, resulting in the increased pristine remnant polarization (2Pr). The pristine value (2Pr) of baseline samples annealed at 500 °C and 600 °C were 11.4 µC/cm2 and 24.4 µC/cm2, respectively. However, with the F-passivation, the 2Pr values were increased to 30.8 µC/cm2 and 48.2 µC/cm2 for 500 °C and 600 °C, respectively. The amount of surface defects and oxygen vacancies are quantitatively confirmed by the conductance method and XPS analysis. However, due to the incorporation of fluorine atoms into the ferroelectric-insulator films, undesirable degradation on endurance characteristics were observed.

Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM.

As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact of structural variations on the electrical characteristics can be more significant than expected. Using a technology computer-aided design (TCAD) tool, the structural variations in BCAT (e.g., the aspect ratio of the BCAT recess-to-gate length, BCAT depth, junction depth, fin width, and fin fillet radius) were simulated to enable a quantitative understanding of its impact on the device characteristics, such as the input/output characteristics, threshold voltage, subthreshold swing, on-/off-current ratio, and drain-induced barrier lowering. This work paves the road for the design of a variation-robust BCAT.

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.

Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages.

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.

Impact of Chamber/Annealing Temperature on the Endurance Characteristic of Zr:HfO2 Ferroelectric Capacitor.

The endurance characteristic of Zr-doped HfO2 (HZO)-based metal-ferroelectric-metal (MFM) capacitors fabricated under various deposition/annealing temperatures in the atomic layer deposition (ALD) process was investigated. The chamber temperature in the ALD process was set to 120 °C, 200 °C, or 250 °C, and the annealing temperature was set to 400 °C, 500 °C, 600 °C, or 700 °C. For the given annealing temperature of 700 °C, the remnant polarization (2Pr) was 17.21 µC/cm2, 26.37 µC/cm2, and 31.8 µC/cm2 at the chamber temperatures of 120 °C, 200 °C, and 250 °C, respectively. For the given/identical annealing temperature, the largest remnant polarization (Pr) was achieved when using the chamber temperature of 250 °C. At a higher annealing temperature, the grain size in the HZO layer becomes smaller, and thereby, it enables to boost up Pr. It was observed that the endurance characteristics for the capacitors fabricated under various annealing/chamber temperatures were quite different. The different endurance characteristics are due to the oxygen and oxygen vacancies in ferroelectric films, which affects the wakeup/fatigue behaviors. However, in common, all the capacitors showed no breakdown for an externally applied pulse (up to 108 cycles of the pulse).

Ferroelectric Field-Effect-Transistor Integrated with Ferroelectrics Heterostructure.

To address the demands of emerging data-centric computing applications, ferroelectric field-effect transistors (Fe-FETs) are considered the forefront of semiconductor electronics owing to their energy and area efficiency and merged logic-memory functionalities. Herein, the fabrication and application of an Fe-FET, which is integrated with a van der Waals ferroelectrics heterostructure (CuInP2 S6 /α-In2 Se3 ), is reported. Leveraging enhanced polarization originating from the dipole coupling of CIPS and α-In2 Se3 , the fabricated Fe-FET exhibits a large memory window of 14.5 V at VGS = ±10 V, reaching a memory window to sweep range of ≈72%. Piezoelectric force microscopy measurements confirm the enhanced polarization-induced wider hysteresis loop of the double-stacked ferroelectrics compared to single ferroelectric layers. The Landau-Khalatnikov theory is extended to analyze the ferroelectric characteristics of a ferroelectric heterostructure, providing detailed explanations of the hysteresis behaviors and enhanced memory window formation. The fabricated Fe-FET shows nonvolatile memory characteristics, with a high on/off current ratio of over 106 , long retention time (>104 s), and stable cyclic endurance (>104 cycles). Furthermore, the applicability of the ferroelectrics heterostructure is investigated for artificial synapses and for hardware neural networks through training and inference simulation. These results provide a promising pathway for exploring low-dimensional ferroelectronics.

Strain-Dependent Photoacoustic Characteristics of Free-Standing Carbon-Nanocomposite Transmitters.

In this paper we demonstrate strain-dependent photoacoustic (PA) characteristics of free-standing nanocomposite transmitters that are made of carbon nanotubes (CNT) and candle soot nanoparticles (CSNP) with an elastomeric polymer matrix. We analyzed and compared PA output performances of these transmitters which are prepared first on glass substrates and then in a delaminated free-standing form for strain-dependent characterization. This confirms that the nanocomposite transmitters with lower concentration of nanoparticles exhibit more flexible and stretchable property in terms of Young's modulus in a range of 4.08-10.57 kPa. Then, a dynamic endurance test was performed revealing that both types of transmitters are reliable with pressure amplitude variation as low as 8-15% over 100-800 stretching cycles for a strain level of 5-28% with dynamic endurance in range of 0.28-2.8%. Then, after 2000 cycles, the transmitters showed pressure amplitude variation of 6-29% (dynamic endurance range of 0.21-1.03%) at a fixed strain level of 28%. This suggests that the free-standing nanocomposite transmitters can be used as a strain sensor under a variety of environments providing robustness under repeated stretching cycles.

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device.

In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

A Soft Pressure Sensor Array Based on a Conducting Nanomembrane.

Although skin-like pressure sensors exhibit high sensitivity with a high performance over a wide area, they have limitations owing to the critical issue of being linear only in a narrow strain range. Various strategies have been proposed to improve the performance of soft pressure sensors, but such a nonlinearity issue still exists and the sensors are only effective within a very narrow strain range. Herein, we fabricated a highly sensitive multi-channel pressure sensor array by using a simple thermal evaporation process of conducting nanomembranes onto a stretchable substrate. A rigid-island structure capable of dissipating accumulated strain energy induced by external mechanical stimuli was adopted for the sensor. The performance of the sensor was precisely controlled by optimizing the thickness of the stretchable substrate and the number of serpentines of an Au membrane. The fabricated sensor exhibited a sensitivity of 0.675 kPa-1 in the broad pressure range of 2.3-50 kPa with linearity (~0.990), and good stability (>300 Cycles). Finally, we successfully demonstrated a mapping of pressure distribution.

Experimental study of threshold voltage shift for Si:HfO2based ferroelectric field effect transistor.

For a given three different Si doping concentrations at room and high temperatures, the threshold voltage shift (ΔVth) on silicon-doped hafnium-oxide-based ferroelectric field effect transistor (FeFET) is experimentally investigated. It turned out that charge trapping in the gate stack of FeFET (versus polarization switching in the gate stack of FeFET) adversely affects ΔVth. Charge trapping causes the positive ΔVth, while polarization switching causes the negative ΔVth. The dominance of polarization switching is predominantly determined by the total remnant polarization (2Pr), which can be controlled by adjusting Si doping concentration in the hafnium-oxide layer. As the Si doping concentration increases from 2.5% to 3.6%, and 5.0%, 2Prdecreases 19.8µC cm-2to 15.25µC cm-2, and 12.5µC cm-2, which leads to ΔVthof -0.8 V, -0.09 V, and +0.1 V, respectively, at room temperature. At high temperature, the effect of polarization switching is degraded due to the decreasedPr, while the effect of charge trapping is very independent of temperature. For those three different Si doping concentrations (i.e. 2.5%, 3.6%, and 5.0%), at the high temperature, ΔVthof FeFET is -0.675 V, -0.075 V, and +0.15 V, respectively. This experimental work should provide an insight for designing FeFET for memory and logic applications.

Recent Studies on Supercapacitors with Next-Generation Structures.

Supercapacitors have shown great potential as a possible solution to the increasing global demand for next-generation energy storage systems. Charge repositioning is based on physical or chemical mechanisms. There are three types of supercapacitors-the electrochemical double layer, the pseudocapacitor, and a hybrid of both. Each type is further subdivided according to the material used. Herein, a detailed overview of the working mechanism as well as a new method for capacitance enhancement are presented.

Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor.

In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key knob in designing the devices. It is experimentally observed that the hysteresis window of FE-FDSOI/FE-FinFET is decreased with (i) increasing the area of the ferroelectric capacitor and/or (ii) decreasing the gate area of baseline FET. The way how to control the hysteresis window of FE-FDSOI/FE-FinFET is proposed and discussed in detail.

Investigation on Threshold Voltage Adjustment of Threshold Switching Devices with HfO2/Al2O3 Superlattice on Transparent ITO/Glass Substrate.

Threshold voltage adjustment in threshold switching (TS) devices with HfO2/Al2O3 superlattice (by means of changing the cycle ratio of HfO2 to Al2O3 in atomic layer deposition) is investigated to implement a transparent cross-point array. TS devices with different cycle ratios (i.e., 3:1, 3:2, and 3:3) were fabricated and studied. The threshold voltage of the devices was increased from 0.9 V to 3.2 V, as the relative contents of Al2O3 layer in the superlattice were increased. At the same time, it is demonstrated that the off-resistance values of the devices were enhanced from 2.6 109 to 6 1010 as the atomic layer deposition (ALD) cycle ratio of HfO2 to Al2O3 layer was adjusted from 3:1 to 3:3. However, the hold voltage and the on-current values were almost identical for the three devices. These results can be understood using the larger barrier height of Al2O3 layer than that of HfO2 layer.

Superaerophobic hydrogels for enhanced electrochemical and photoelectrochemical hydrogen production.

The efficient removal of gas bubbles in (photo)electrochemical gas evolution reactions is an important but underexplored issue. Conventionally, researchers have attempted to impart bubble-repellent properties (so-called superaerophobicity) to electrodes by controlling their microstructures. However, conventional approaches have limitations, as they are material specific, difficult to scale up, possibly detrimental to the electrodes' catalytic activity and stability, and incompatible with photoelectrochemical applications. To address these issues, we report a simple strategy for the realization of superaerophobic (photo)electrodes via the deposition of hydrogels on a desired electrode surface. For a proof-of-concept demonstration, we deposited a transparent hydrogel assembled from M13 virus onto (photo)electrodes for a hydrogen evolution reaction. The hydrogel overlayer facilitated the elimination of hydrogen bubbles and substantially improved the (photo)electrodes' performances by maintaining high catalytic activity and minimizing the concentration overpotential. This study can contribute to the practical application of various types of (photo)electrochemical gas evolution reactions.

Rhenium Diselenide (ReSe2) Near-Infrared Photodetector: Performance Enhancement by Selective p-Doping Technique.

In this study, a near-infrared photodetector featuring a high photoresponsivity and a short photoresponse time is demonstrated, which is fabricated on rhenium diselenide (ReSe2) with a relatively narrow bandgap (0.9-1.0 eV) compared to conventional transition-metal dichalcogenides (TMDs). The excellent photo and temporal responses, which generally show a trade-off relation, are achieved simultaneously by applying a p-doping technique based on hydrochloric acid (HCl) to a selected ReSe2 region. Because the p-doping of ReSe2 originates from the charge transfer from un-ionized Cl molecules in the HCl to the ReSe2 surface, by adjusting the concentration of the HCl solution from 0.1 to 10 m, the doping concentration of the ReSe2 is controlled between 3.64 × 1010 and 3.61 × 1011 cm-2. Especially, the application of the selective HCl doping technique to the ReSe2 photodetector increases the photoresponsivity from 79.99 to 1.93 × 103 A W-1, and it also enhances the rise and decay times from 10.5 to 1.4 ms and from 291 to 3.1 ms, respectively, compared with the undoped ReSe2 device. The proposed selective p-doping technique and its fundamental analysis will provide a scientific foundation for implementing high-performance TMD-based electronic and optoelectronic devices.

Comprehensive study of high pressure annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films.

Thin films of ferroelectric materials are potential candidates to be implemented in the unfolding of a new paradigm in high-density memory devices. As the thickness of these films reaches the sub-10 nm level, the interface properties between the electrode and ferroelectric material undergo significant changes that play a crucial role in governing the ferroelectric behavior. The present state-of-the-art approach presents a detailed investigation of different high pressure annealing (HPA) conditions through simulation studies. The simulation studies were performed using Landau-Khalatnikov equations, with Landau's parameters calculated using the least regression method as described in the Method S1. The extracted coefficients were used to determine various relationships (free energy, ferroelectric potential and negative capacitance) with which to observe the impact of HPA on the negative capacitance (NC) effect on account of the majority ferroelectric phase. To verify the simulation results, pulse transient switching measurements were conducted using Pt/Ti/TiN/Hf0.5Zr0.5O2/TiN-based metal-ferroelectric-metal (MFM) devices to study the coercive field, interfacial capacitance and load resistance behavior. The results suggest that the non-ferroelectric portion (t-phase) coexists with the ferroelectric (o-phase) within the thin layer of the MFM capacitor adjacent to TiN electrode, which undergoes a phase transformation from the t-phase to the o-phase when exposed to different HPA conditions as well as electric field cycling during PS measurements. The simulation and experimental results confirm that the 550 °C at 50 atm N2 environment provides the best possibility of achieving the highest ferroelectric characteristics with the lowest proportion of the non-ferroelectric phase and thus the maximum NC effect as well.

Polarity control in a single transition metal dichalcogenide (TMD) transistor for homogeneous complementary logic circuits.

Recently, there have been various attempts to demonstrate the feasibility of transition metal dichalcogenide (TMD) transistors for digital logic circuits. A complementary inverter circuit, which is a basic building block of a logic circuit, was implemented in earlier works by heterogeneously integrating n- and p-channel transistors fabricated on different TMD materials. Subsequently, to simplify the circuit design and fabrication process, complementary inverters were constructed on single-TMD materials using ambipolar transistors. However, continuous transition from the electron-conduction to the hole-conduction state in the ambipolar devices led to the problem of a high leakage current. Here, we report a polarity-controllable TMD transistor that can operate as both an n- and a p-channel transistor with a low leakage current of a few picoamperes. The device polarity can be switched simply by converting the sign of the drain voltage. This is because a metal-like tungsten ditelluride (WTe2) with a low carrier concentration is used as a drain contact, which subsequently allows selective carrier injection at the palladium/tungsten diselenide (WSe2) junction. In addition, by using the operating principle of the polarity-controllable transistor, we demonstrate a complementary inverter circuit on a single TMD channel material (WSe2), which exhibits a very low static power consumption of a few hundred picowatts. Finally, we confirm the expandability of this polarity-controllable transistor toward more complex logic circuits by presenting the proper operation of a three-stage ring oscillator.