Data Transformation in the Processing of Neuronal Signals: A Powerful Tool to Illuminate Informative Contents.

Neuroscientists seek efficient solutions for deciphering the sophisticated unknowns of the brain. Effective development of complicated brain-related tools is the focal point of research in neuroscience and neurotechnology. Thanks to today's technological advancements, the physical development of high-density and high-resolution neural interfaces has been made possible. This is where the critical bottleneck in receiving the expected functionality from such devices shifts to transferring, processing, and subsequently analyzing the massive neurophysiological extra-cellular data recorded. To respond to this inevitable concern, a spectrum of neuronal signal processing techniques have been proposed to extract task-related informative content of the signals conveying neuronal activities, and eliminate the irrelevant contents. Such techniques provide powerful tools for a wide range of neuroscience research, from low-level perception to high-level cognition. Data transformations are among the most efficient processing techniques that serve this purpose by properly changing the data representation. Mapping the data from its original domain (i.e., the time-space domain) to a new representational domain, data transformations change the viewing angle of observing the informative content of the data. This paper reviews the employment of data transformations in order to process neuronal signals and their three key applications, including spike detection, spike sorting, and data compression.

Intertwined-pulse modulation for compressive data telemetry.

This paper presents a novel approach for anisochronous pulse-based modulation. In the proposed approach, referred to as the intertwined-pulse modulation (IPM), every pair of consecutive symbols overlap in time. This allows for shortening the time allocated for the transmission of the symbols, hence achieving temporal compaction while the data goes through the line encoding step in a digital communication system. The IPM is also uniquely superior to other existing anisochronous pulse-based modulation schemes in the fact that it exhibits robust symbol error rate against unwanted variations in both rise/fall times of the pulses in the modulated waveform, and in the threshold level used for data detection on the receiver side. An experimental setup was developed to implement an IPM encoder using standard digital hardware, and an IPM decoder as a part of the receiver system in software. According to the experimental results (supported by simulation results and theoretical studies), for the data mean value of mid-full-scale range, the proposed IPM scheme exhibits a time-domain compaction rate of up to 209.2%.

Wireless, miniaturized, semi-implantable electrocorticography microsystem validated in vivo.

This paper reports on the design, development, and test of a multi-channel wireless micro-electrocorticography (µECoG) system. The system consists of a semi-implantable, ultra-compact recording unit and an external unit, interfaced through a 2.4 GHz radio frequency data telemetry link with 2 Mbps (partially used) data transfer rate. Encased in a 3D-printed 2.9 cm × 2.9 cm × 2.5 cm cubic package, the semi-implantable recording unit consists of a microelectrode array, a vertically-stacked PCB platform containing off-the-shelf components, and commercially-available small-size 3.7-V, 50 mAh lithium-ion batteries. Two versions of microelectrode array were developed for the recording unit: a rigid 4 × 2 microelectrode array, and a flexible 12 × 6 microelectrode array, 36 of which routed to bonding pads for actual recording. The external unit comprises a transceiver board, a data acquisition board, and a host computer, on which reconstruction of the received signals is performed. After development, assembly, and integration, the system was tested and validated in vivo on anesthetized rats. The system successfully recorded both spontaneous and evoked activities from the brain of the subject.

Spike Detection Technique Based on Spike Augmentation with Low Computational and Hardware Complexity.

In this paper, a method for the detection and subsequently extraction of neural spikes in an intra-cortically recorded neural signal is proposed. This method distinguishes spikes from the background noise based on the natural difference between their time-domain amplitude variation patterns. According to this difference, a spike mask is generated, which takes on large values over the course of spikes, and much smaller values for the background noise. The "high" part of this mask is designed to be wide enough to contain a complete spike. By multiplying the input neural signal with the spike mask, spikes are amplified with a large factor while the background noise is not. The result is a spike-augmented signal with significantly larger signal-to-noise ratio, on which spike detection is performed much more easily and accurately. According to this detection mechanism, spikes of the original neural signal are extracted.Clinical Relevance-This paper presents an automatic spike detection technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.

Spatial Redundancy Reduction in Multi-Channel Implantable Neural Recording Microsystems.

This paper introduces a lossless approach for data reduction in multi-channel neural recording microsystems. The proposed approach benefits from eliminating the redundancy that exists in the signals recorded from the same space in the brain, e.g., local field potentials in intra-cortical recording from neighboring recording sites. In this approach, a single baseline component is extracted from the original neural signals, which is treated as the component all the channels share in common. What remains is a set of channel-specific difference components, which are much smaller in word length compared to the sample size of the original neural signals. To make the proposed approach more efficient in data reduction, length of the difference component words is adaptively determined according to their instantaneous amplitudes. This approach is low in both computational and hardware complexity, which introduces it as an attractive suggestion for high-density neural recording brain implants. Applied on multi-channel neural signals intra-cortically recorded using 16 multi-electrode array, the data is reduced by around 48%. Designed in TSMC 130-nm standard CMOS technology, hardware implementation of this technique for 16 parallel channels occupies a silicon area of 0.06 mm2, and dissipates 6.4 µW of power per channel when operates at VDD=1.2V and 400 kHz.Clinical Relevance- This paper presents a lossless data reduction technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.

Hardware and Power-Efficient Compression Technique Based on Discrete Tchebichef Transform for Neural Recording Microsystems.

In this paper a new compression technique based on the discrete Tchebichef transform is presented. To comply with strict on-implant hardware implementation requirements, such as low power dissipation and small silicon area consumption, the discrete Tchebichef transform is modified and truncated. An algorithm is proposed to generate approximate transform matrices capable of truncation without suffering from destructive energy leakage among the coefficients. This is achieved by preserving orthogonality of the basis functions that convey majority portion of the signal energy. Based on the presented algorithm, a new truncated transformation matrix is proposed, which reduces the hardware complexity by up to 74% compared to that of the original transform. Hardware implementation of the proposed neural signal compression technique is prototyped using standard digital hardware. With pre-recorded neural signals as the input, compression rate of 26.15 is achieved while the root-mean-square of error is kept as low as 1.1%.Clinical Relevance- This paper proposes a technique for data compression in high-density neural recording brain implants, along with a power- and area-efficient hardware implementation. From among clinical applications of such implants one can point to neuro-prostheses, and brain-machine interfaces for therapeutic purposes.

A framework for on-implant spike sorting based on salient feature selection.

On-implant spike sorting methods employ static feature extraction/selection techniques to minimize the hardware cost. Here we propose a novel framework for real-time spike sorting based on dynamic selection of features. We select salient features that maximize the geometric-mean of between-class distances as well as the associated homogeneity index effectively to best discriminate spikes for classification. Wave-shape classification is performed based on a multi-label window discrimination approach. An external module calculates the salient features and discrimination windows through optimizing a replica of the on-implant operation, and then configures the on-implant spike sorter for real-time online operation. Hardware implementation of the on-implant online spike sorter for 512 channels of concurrent extra-cellular neural signals is reported, with an average classification accuracy of ~88%. Compared with other similar methods, our method shows reduction in classification error by a factor of ~2, and also reduction in the required memory space by a factor of ~5.

Modeling and Characterization of Capacitive Elements With Tissue as Dielectric Material for Wireless Powering of Neural Implants.

This paper reports on the modeling and characterization of capacitive elements with tissue as the dielectric material, representing the core building block of a capacitive link for wireless power transfer to neural implants. Each capacitive element consists of two parallel plates that are aligned around the tissue layer and incorporate a grounded, guarded, capacitive pad to mitigate the adverse effect of stray capacitances and shield the plates from external interfering electric fields. The plates are also coated with a biocompatible, insulating, coating layer on the inner side of each plate in contact with the tissue. A comprehensive circuit model is presented that accounts for the effect of the coating layers and is validated by measurements of the equivalent capacitance as well as impedance magnitude/phase of the parallel plates over a wide frequency range of 1 kHz-10 MHz. Using insulating coating layers of Parylene-C at a thickness of and Parylene-N at a thickness of deposited on two sets of parallel plates with different sizes and shapes of the guarded pad, our modeling and characterization results accurately capture the effect of the thickness and electrical properties of the coating layers on the behavior of the capacitive elements over frequency and with different tissues.

Versatile Stimulation Back-End With Programmable Exponential Current Pulse Shapes for a Retinal Visual Prosthesis.

This paper reports on the design, implementation, and test of a stimulation back-end, for an implantable retinal prosthesis. In addition to traditional rectangular pulse shapes, the circuit features biphasic stimulation pulses with both rising and falling exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is used as a wide-swing, high-output-resistance stimulation current driver, delivering stimulation current pulses of up to ±96 µA to the target tissue. Duration of the generated current pulses is programmable within the range of 100 µs to 3 ms. Current-mode digital-to-analog converters (DACs) are used to program the amplitudes of the stimulation pulses. Fabricated using the IBM 130 nm process, the circuit consumes 1.5×1.5 mm2 of silicon area. According to the measurements, the DACs exhibit DNL and INL of 0.23 LSB and 0.364 LSB, respectively. Experimental results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance of as high as 25 k Ω. Maximum power consumption of the proposed design is 3.4 mW when delivering biphasic rectangular pulses to the target load. A charge pump block is in charge of the upconversion of the standard 1.2-V supply voltage to ±3.3V.

Fully-implantable, multi-channel, microstimulator with tracking supply ribbon and energy recovery.

This paper proposes a novel energy-efficient approach dedicated to high-density implantable stimulators such as visual prostheses. Energy efficiency of the approach proposed in this work is achieved through two ideas: the `tracking supply ribbon' technique, and `reverse charge pumping'. The proposed approach is implemented, in the multichannel case, in such a way that power efficiency of each stimulation channel is enhanced according to its specific voltage/current condition and independently from other channels. Based on the proposed approach, a 16-channel stimulation backend for a visual prosthesis was designed and simulated in the transistor level in a low-voltage 0.18µm triple-well CMOS technology, occupying 1 mm2 of silicon area. According to post-layout simulation results, power savings of up to 74.9% are achieved compared to the conventional output stage with a constant supply voltage.

A method for compression of intra-cortically-recorded neural signals dedicated to implantable brain-machine interfaces.

This paper proposes an efficient data compression technique dedicated to implantable intra-cortical neural recording devices. The proposed technique benefits from processing neural signals in the Discrete Haar Wavelet Transform space, a new spike extraction approach, and a novel data framing scheme to telemeter the recorded neural information to the outside world. Based on the proposed technique, a 64-channel neural signal processor was designed and prototyped as a part of a wireless implantable extra-cellular neural recording microsystem. Designed in a 0.13- µ m standard CMOS process, the 64-channel neural signal processor reported in this paper occupies ∼ 0.206 mm(2) of silicon area, and consumes 94.18 µW when operating under a 1.2-V supply voltage at a master clock frequency of 1.28 MHz.

Data compression in brain-machine/computer interfaces based on the Walsh-Hadamard transform.

This paper reports on the application of the Walsh-Hadamard transform (WHT) for data compression in brain-machine/brain-computer interfaces. Using the proposed technique, the amount of the neural data transmitted off the implant is compressed by a factor of at least 63 at the expense of as low as 4.66% RMS error between the signal reconstructed on the external host and the original neural signal on the implant side. Based on the proposed idea, a 128-channel WHT processor was designed in a 0.18- µm CMOS process occupying 1.64 mm(2) of silicon area. The circuit consumes 81 µW (0.63 µW per channel) from a 1.8-V power supply at 250 kHz. A prototype of the proposed processor was implemented and successfully tested using prerecorded neural signals.

Nonlinear Signal-Specific ADC for Efficient Neural Recording in Brain-Machine Interfaces.

A nonlinear ADC dedicated to the digitization of neural signals in implantable brain-machine interfaces is presented. Benefitting from an exponential quantization function, effective resolution of the proposed ADC in the digitization of action potentials is almost 2 bits more than its physical number of bits. Hence, it is shown in this paper that the choice of a proper nonlinear quantization function helps reduce the outgoing bit rate carrying the recorded neural data. Another major benefit of digitizing neural signals using the proposed signal-specific ADC is the considerable reduction in the background noise of the neural signal. The 8-b exponential ADC reported in this paper digitizes large action potentials with maximum resolution of 10.5 bits , while quantizing the small background noise is performed with a resolution of as low as 3 bits. Fully-integrated version of the circuit was designed and fabricated in a 0.18-µm CMOS process, occupying 0.036 mm(2) silicon area. Designed based on a two-step successive-approximation register ADC architecture, the proposed ADC employs a piecewise-linear approximation of the target exponential function for quantization. Operating at a sampling frequency of 25 kS/s (typical for intra-cortical neural recording) and with a supply voltage of 1.8 V, the entire chip, including the ADC and reference circuits, dissipates 87.2 µW. According to the experiments, Noise-Content-Reduction Ratio (NCRR) of the ADC is 41.1 dB.

Programmable high-output-impedance, large-voltage compliance, microstimulator for low-voltage biomedical applications.

This paper reports on the design of a programmable, high output impedance, large voltage compliance microstimulator for low-voltage biomedical applications. A 6-bit binary-weighted digital to analog converter (DAC) is used to generate biphasic stimulus current pulses. A compact current mirror with large output voltage compliance and high output resistance conveys the current pulses to the target tissue. Designed and simulated in a standard 0.18µm CMOS process, the microstimulator circuit is capable of delivering a maximum stimulation current of 160µA to a 10-kΩ resistive load. Operated at a 1.8-V supply voltage, the output stage exhibits a voltage compliance of 1.69V and output resistance of 160MΩ at full scale stimulus current. Layout of the core microelectrode circuit measures 25.5µm×31.5µm.

Wearable, battery-powered, wireless, programmable 8-channel neural stimulator.

In this paper, a wearable, battery-powered, low-power, low-size, cost-efficient, fully programmable neural stimulator is presented. The system comprises a wearable stimulator module and an external controller. To receive the settings required for the operation of the system, the wearable module is programmed through wireless connection to the external controller. Implemented using off-the-shelf components, the wearable neural stimulator weighs 60 g and measures 9 cm × 5 cm × 2 cm. The system is capable of generating independent biphasic stimulations on 8 channels with programmable amplitudes and timings. The neural stimulator consumes about 1.5 mW in the power-down mode and about 51.2 mW in the active mode when all the 8 channels are active. For in-vivo experiments, the system was used to stimulate motor cortex of an anesthetized rat fixed in a stereotaxic instrument.

A 64-channel neural signal processor/ compressor based on Haar wavelet transform.

A signal processor/compressor dedicated to implantable neural recording microsystems is presented. Signal compression is performed based on Haar wavelet. It is shown in this paper that, compared to other mathematical transforms already used for this purpose, compression of neural signals using this type of wavelet transform can be of almost the same quality, while demanding less circuit complexity and smaller silicon area. Designed in a 0.13-µm standard CMOS process, the 64-channel 8-bit signal processor reported in this paper occupies 113 µm x 110 µm of silicon area. It operates under a 1.8-V supply voltage at a master clock frequency of 3.2 MHz.

Flexible PET/ITO electrode array for implantable biomedical applications.

Flexible PET/ITO (PolyEthylene Terephthalate/ Indium Tin Oxide) implantable electrode array for spinal cord stimulation and retina prosthesis have been developed. The electrode array is fabricated on a thin PET/ITO substrate and encapsulated with insulating material, SU-8. The PET substrate made electrodes flexible so that they could shape to contoured tissues. A layer of gold on the stimulation sites served to reduce the electrode/tissue interface impedance. Prototypes of 1 × 8 and 3 × 8 electrode arrays are fabricated for monophasic and biphasic stimulation of spinal cord respectively. The exposed electrode dimensions are 3 mm² for monophasic and 6 mm² for biphasic stimulation with 100 µm of interconnection paths. The prototype of 4 × 4 electrode arrays were also fabricated with the same process for retinal prosthesis with exposed electrode diameter of 125 µm. To verify the functionality of the subdural electrodes, the electrochemical impedance spectroscopy was measured. The electrode/tissue impedance was 500 Ω at 1KHz for 3 mm² area.

Design of double layer printed spiral coils for wirelessly-powered biomedical implants.

In this paper employing double layer printed spiral coils (PSCs) is proposed for wireless power transmission in implantable biomedical applications. Detailed modeling of this type of PSCs is presented. Both calculations and measurements of fabricated double layer PSCs indicate that this structure can decrease the size of typical single layer PSCs without any change in the most important parameters of the coils, such as quality factor. Also, it is shown that with equal PSC dimensions and design parameters, double layer PSCs achieve significantly higher inductances and quality factors. Ultimately, a pair of double layer PSCs with a distance of 5 mm in air is used in an inductive link. The power transfer efficiency of this link is about 79.8% with a carrier frequency of 5 MHz and coupling coefficient of 0.189.

Adaptive spike detection method based on capacitor arrays dedicated to implantable neural recording microsystems.

An analog spike detector circuit is presented, which adaptively generates a threshold level for spike detection based on hard-thresholding. Operation of the circuit was tested not only with a neural signal obtained from real in-vivo recording from a live animal, but also with a large sinusoidal baseline variation intentionally added to examine the capability of the circuit to track baseline variations as large as 50mV. The circuit runs at 3.3V supply voltage and dissipates 270 microW.