Electrical stress effect on on-current of MILC poly-Si thin-film transistors.

In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to hot-electron trap at the drain junction. The computer simulation revealed the fact that the improvement mechanism can be reproduced by effective channel length shortening. It turns out that analysis of the capacitance and output characteristics supports this model.

Tilted back exposure for lightly doped drain structure in metal induced lateral crystallization poly Si thin film transistors.

It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In this work, a simple method has been introduced for formation of LDD structure in poly Si TFTs, Tilted Back Exposure (TBE) technique. It has been found that asymmetry patterns can be realized with TBE process and submicron accuracy can be easily achieved by adjusting the angle between the substrate and light source. The LDD TFTs using TBE process shows almost the same electrical properties as the LDD TFTs using an additional separate LDD Mask.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

Electrical activation of ion mass doped phosphorous.

In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application. In case of a single crystal substrate, the resistance was measured to be 20-50 omega/square depending on the dose and annealing temperature. In case of poly crystal, we could observe segregation of the dopant at grain boundaries, which caused increase of the resistance with increase of annealing temperature. In case of amorphous silicon thin film, this phenomenon could not be observed due to lack of the grain boundaries and the minimum resistance of this work was about 300 omega/square, which was about the same to that in a poly silicon thin film.

Leakage current behavior of the bottom gate poly thin-film transistor fabricated by copper damascene process.

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing. The results simulated by 3D electric field simulator demonstrate that the structure of planarized gate in bottom-gate TFT can effectively reduce the electric field causing the field emission between the gate and the drain.

Effect of lightly doped drain structure on P-channel metal induced lateral crystallization thin film transistors.

A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.5 microm, and depending on the location of the V(d) application between the source and drain, an LDD or Lightly Doped Source (LDS) structure can be realized on the same TFT. In this way, we can make a perfect comparison between these two structures. It turned out that the LDD is mainly responsible for the low leakage current, and no more than 0.5 microm of the lightly doped region is necessary to lower the leakage current down to less than 5 x 10(-11) amps at V(d) = 10 volts. Typically, the on-current of MILC TFT is more than 10(-4) amps, but 2.5 microm LDS decreases it to below 10(-7) amps.