Machine Learning Algorithm for Efficient Design of Separated Buffer Super-Junction IGBT.

An improved structure for an Insulated Gate Bipolar Transistor (IGBT) with a separated buffer layer is presented in order to improve the trade-off between the turn-off loss (Eoff) and on-state voltage (Von). However, it is difficult to set efficient parameters due to the increase in the new buffer doping concentration variable. Therefore, a machine learning (ML) algorithm is proposed as a solution. Compared to the conventional Technology Computer-Aided Design (TCAD) simulation tool, it is demonstrated that incorporating the ML algorithm into the device analysis could make it possible to achieve high accuracy and significantly shorten the simulation time. Specifically, utilizing the ML algorithm could achieve coefficients of determination (R2) of Von and Eoff of 0.995 and 0.968, respectively. In addition, it enables the optimized design to fit the target characteristics. In this study, the structure proposed for the trade-off improvement was targeted to obtain the minimum Eoff at the same Von, especially by adjusting the concentration of the separated buffer. We could improve Eoff by 36.2% by optimizing the structure, which was expected to be improved by 24.7% using the ML approach. In another way, it is possible to inversely design four types of structures with characteristics close to the target characteristics (Eoff = 1.64 µJ, Von = 1.38 V). The proposed method of incorporating machine learning into device analysis is expected to be very strategic, especially for power electronics analysis (where the transistor size is comparatively large and requires significant computation). In summary, we improved the trade-off using a separated buffer, and ML enabled optimization and a more precise design, as well as reverse engineering.

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide.

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor.

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending on the gate voltage, the three variations occur in transfer curves. The first one is the on-state current (ION) variation, the second one is the hump current (IHUMP) variation, and the last one is ambipolar current (IAMB) variation. According to the simulation results, the ION variation is sensitive depending on the size of the tunneling region and could be reduced by increasing the tunneling region. However, the IHUMP and IAMB variations are relatively irrelevant to the size of the tunneling region. In order to analyze the cause of this difference, we investigated the band-to-band tunneling (BTBT) rate according to WFV cases. The results show that when ION is formed in L-shaped TFET, the BTBT rate relies on the WFV in the whole region of the gate because the tunnel barrier is formed in the entire area where the source and the gate meet. On the other hand, when the IHUMP and IAMB are formed in L-shaped TFET, the BTBT rate relies on the WFV in the edge of the gate.

Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation.

In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). In order to investigate electrical and self-heating characteristics of the proposed devices, on-current, off-current, subthreshold swing (SS), and operating temperature were examined by using 3D TCAD simulator and compared with nanowire MOSFET (NW-MOSFET). As a result, a possibility of reducing off-current and operating temperature was demonstrated by using the ONWFET with 40% GCR. Therefore, the ONWFET can save power consumption and serve as low power application such as battery-powered portable electronic devices.

Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect.

In this research, we propose an Integrate-and-fire (I&F) Silicon-on-insulator (SOI) neuron circuit incorporating a Schmitt trigger as an action potential generating component. The Schmitt trigger is composed of four MOSFETs, and it presents hysteresis by controlling the threshold of one of the four MOSFET using back-gate effect. The presented circuit effectively handles input overflow by modulating output pulse duration, thus maintaining Rectified-linear-unit (ReLU) equivalence of I&F spiking neuron. The effect of overflow handling by output pulse modulation was further investigated by comparing the performance of single-layer spiking neural network (SNN) implemented using proposed circuit and conventional circuit. The ex-situ (offline) triained SNN implemented using the proposed circuit showed 1.8%p accuracy improvement in classifying 1000 MNIST handwritten digits compared to one implemented using conventional I&F neuron circuit due to elimination of quantization error.