Highly reproducible and CMOS-compatible VO2-based oscillators for brain-inspired computing.

With remarkable electrical and optical switching properties induced at low power and near room temperature (68 °C), vanadium dioxide (VO2) has sparked rising interest in unconventional computing among the phase-change materials research community. The scalability and the potential to compute beyond the von Neumann model make VO2 especially appealing for implementation in oscillating neural networks for artificial intelligence applications, to solve constraint satisfaction problems, and for pattern recognition. Its integration into large networks of oscillators on a Silicon platform still poses challenges associated with the stabilization in the correct oxidation state and the ability to fabricate a structure with predictable electrical behavior showing very low variability. In this work, the role played by the different annealing parameters applied by three methods (slow thermal annealing, flash annealing, and rapid thermal annealing), following the vanadium oxide atomic layer deposition, on the formation of VO2 grains is studied and an optimal substrate stack configuration that minimizes variability between devices is proposed. Material and electrical characterizations are performed on the different films and a step-by-step recipe to build reproducible VO2-based oscillators is presented, which is argued to be made possible thanks to the introduction of a hafnium oxide (HfO2) layer between the silicon substrate and the vanadium oxide layer. Up to seven nearly identical VO2-based devices are contacted simultaneously to create a network of oscillators, paving the way for large-scale implementation of VO2 oscillating neural networks.

Disorder-Induced Magnetotransport Anomalies in Amorphous and Textured Co1-xSix Semimetal Thin Films.

In recent times the chiral semimetal cobalt monosilicide (CoSi) has emerged as a prototypical, nearly ideal topological conductor hosting giant, topologically protected Fermi arcs. Exotic topological quantum properties have already been identified in CoSi bulk single crystals. However, CoSi is also known for being prone to intrinsic disorder and inhomogeneities, which, despite topological protection, risk jeopardizing its topological transport features. Alternatively, topology may be stabilized by disorder, suggesting the tantalizing possibility of an amorphous variant of a topological metal, yet to be discovered. In this respect, understanding how microstructure and stoichiometry affect magnetotransport properties is of pivotal importance, particularly in case of low-dimensional CoSi thin films and devices. Here we comprehensively investigate the magnetotransport and magnetic properties of ≈25 nm Co1-xSix thin films grown on a MgO substrate with controlled film microstructure (amorphous vs textured) and chemical composition (0.40 < x < 0.60). The resistivity of Co1-xSix thin films is nearly insensitive to the film microstructure and displays a progressive evolution from metallic-like (dρxx/dT > 0) to semiconducting-like (dρxx/dT < 0) regimes of conduction upon increasing the silicon content. A variety of anomalies in the magnetotransport properties, comprising for instance signatures consistent with quantum localization and electron-electron interactions, anomalous Hall and Kondo effects, and the occurrence of magnetic exchange interactions, are attributable to the prominent influence of intrinsic structural and chemical disorder. Our systematic survey brings to attention the complexity and the challenges involved in the prospective exploitation of the topological chiral semimetal CoSi in nanoscale thin films and devices.

A multi-timescale synaptic weight based on ferroelectric hafnium zirconium oxide.

Brain-inspired computing emerged as a forefront technology to harness the growing amount of data generated in an increasingly connected society. The complex dynamics involving short- and long-term memory are key to the undisputed performance of biological neural networks. Here, we report on sub-µm-sized artificial synaptic weights exploiting a combination of a ferroelectric space charge effect and oxidation state modulation in the oxide channel of a ferroelectric field effect transistor. They lead to a quasi-continuous resistance tuning of the synapse by a factor of 60 and a fine-grained weight update of more than 200 resistance values. We leverage a fast, saturating ferroelectric effect and a slow, ionic drift and diffusion process to engineer a multi-timescale artificial synapse. Our device demonstrates an endurance of more than 10 10 cycles, a ferroelectric retention of more than 10 years, and various types of volatility behavior on distinct timescales, making it well suited for neuromorphic and cognitive computing.

Selective electrodeposition of indium microstructures on silicon and their conversion into InAs and InSb semiconductors.

The idea of benefitting from the properties of III-V semiconductors and silicon on the same substrate has been occupying the minds of scientists for several years. Although the principle of III-V integration on a silicon-based platform is simple, it is often challenging to perform due to demanding requirements for sample preparation rising from a mismatch in physical properties between those semiconductor groups (e.g. different lattice constants and thermal expansion coefficients), high cost of device-grade materials formation and their post-processing. In this paper, we demonstrate the deposition of group-III metal and III-V semiconductors in microfabricated template structures on silicon as a strategy for heterogeneous device integration on Si. The metal (indium) is selectively electrodeposited in a 2-electrode galvanostatic configuration with the working electrode (WE) located in each template, resulting in well-defined In structures of high purity. The semiconductors InAs and InSb are obtained by vapour phase diffusion of the corresponding group-V element (As, Sb) into the liquified In confined in the template. We discuss in detail the morphological and structural characterization of the synthesized In, InAs and InSb crystals as well as chemical analysis through scanning electron microscopy (SEM), scanning transmission electron microscopy (TEM/STEM), and energy-dispersive X-ray spectroscopy (EDX). The proposed integration path combines the advantage of the mature top-down lithography technology to define device geometries and employs economic electrodeposition (ED) and vapour phase processes to directly integrate difficult-to-process materials on a silicon platform.

Structural Assessment of Interfaces in Projected Phase-Change Memory.

Non-volatile memories based on phase-change materials have gained ground for applications in analog in-memory computing. Nonetheless, non-idealities inherent to the material result in device resistance variations that impair the achievable numerical precision. Projected-type phase-change memory devices reduce these non-idealities. In a projected phase-change memory, the phase-change storage mechanism is decoupled from the information retrieval process by using projection of the phase-change material's phase configuration onto a projection liner. It has been suggested that the interface resistance between the phase-change material and the projection liner is an important parameter that dictates the efficacy of the projection. In this work, we establish a metrology framework to assess and understand the relevant structural properties of the interfaces in thin films contained in projected memory devices. Using X-ray reflectivity, X-ray diffraction and transmission electron microscopy, we investigate the quality of the interfaces and the layers' properties. Using demonstrator examples of Sb and Sb2Te3 phase-change materials, new deposition routes as well as stack designs are proposed to enhance the phase-change material to a projection-liner interface and the robustness of material stacks in the devices.

Waveguide coupled III-V photodiodes monolithically integrated on Si.

The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results.

Semiconductor Epitaxy in Superconducting Templates.

Integration of high-quality semiconductor-superconductor devices into scalable and complementary metal-oxide-semiconductor compatible architectures remains an outstanding challenge, currently hindering their practical implementation. Here, we demonstrate growth of InAs nanowires monolithically integrated on Si inside lateral cavities containing superconducting TiN elements. This technique allows growth of hybrid devices characterized by sharp semiconductor-superconductor interfaces and with alignment along arbitrary crystallographic directions. Electrical characterization at low temperature reveals proximity induced superconductivity in InAs via a transparent interface.

Learning-based defect recognition for quasi-periodic HRSTEM images.

Controlling crystalline material defects is crucial, as they affect properties of the material that may be detrimental or beneficial for the final performance of a device. Defect analysis on the sub-nanometer scale is enabled by high-resolution scanning transmission electron microscopy (HRSTEM), where the identification of defects is currently carried out based on human expertise. However, the process is tedious, highly time consuming and, in some cases, yields ambiguous results. Here we propose a semi-supervised machine learning method that assists in the detection of lattice defects from atomic resolution HRSTEM images. It involves a convolutional neural network that classifies image patches as defective or non-defective, a graph-based heuristic that chooses one non-defective patch as a model, and finally an automatically generated convolutional filter bank, which highlights symmetry breaking such as stacking faults, twin defects and grain boundaries. Additionally, we suggest a variance filter to segment amorphous regions and beam defects. The algorithm is tested on III-V/Si crystalline materials and successfully evaluated against different metrics and a baseline approach, showing promising results even for extremely small training data sets and for noise compromised images. By combining the data-driven classification generality, robustness and speed of deep learning with the effectiveness of image filters in segmenting faulty symmetry arrangements, we provide a valuable open-source tool to the microscopist community that can streamline future HRSTEM analyses of crystalline materials.

Scaling of metal-clad InP nanodisk lasers: optical performance and thermal effects.

A key component for optical on-chip communication is an efficient light source. However, to enable low energy per bit communication and local integration with Si CMOS, devices need to be further scaled down. In this work, we fabricate micro- and nanolasers of different shapes in InP by direct wafer bonding on Si. Metal-clad cavities have been proposed as means to scale dimensions beyond the diffraction limit of light by exploiting hybrid photonic-plasmonic modes. Here, we explore the size scalability of whispering-gallery mode light sources by cladding the sidewalls of the device with Au. We demonstrate room temperature lasing upon optical excitation for Au-clad devices with InP diameters down to 300 nm, while the purely photonic counterparts show lasing only down to 500 nm. Numerical thermal simulations support the experimental findings and confirm an improved heat-sinking capability of the Au-clad devices, suggesting a reduction in device temperature of 450 - 500 K for the metal-clad InP nanodisk laser, compared to the one without Au. This would provide substantial performance benefits even in the absence of a plasmonic mode. These results give an insight into the benefits of metal-clad designs to downscale integrated lasers on Si.

Electrodeposition as an Alternative Approach for Monolithic Integration of InSb on Silicon.

High-performance electronics would greatly benefit from a versatile III-V integration process on silicon. Unfortunately, integration using hetero epitaxy is hampered by polarity, lattice, and thermal expansion mismatch. This work proposes an alternative concept of III-V integration combining advantages of pulse electrodeposition, template-assisted selective epitaxy, and recrystallization from a melt. Efficient electrodeposition of nano-crystalline and stochiometric InSb in planar templates on Si (001) is achieved. The InSb deposits are analysed by high resolution scanning transmission electron microscopy (HR-STEM) and energy-dispersive X-ray spectroscopy (EDX) before and after melting and recrystallization. The results show that InSb can crystallise epitaxially on Si with the formation of stacking faults. Furthermore, X-ray photoelectron (XPS) and Auger electron (AE) spectroscopy analysis indicate that the InSb crystal size is limited by the impurity concentration resulting from the electrodeposition process.

Hybrid III-V Silicon Photonic Crystal Cavity Emitting at Telecom Wavelengths.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 µm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.

Spatially resolved thermoelectric effects in operando semiconductor-metal nanowire heterostructures.

The thermoelectric properties of a nanoscale germanium segment connected by aluminium nanowires are studied using scanning thermal microscopy. The germanium segment of 168 nm length features atomically sharp interfaces to the aluminium wires and is surrounded by an Al2O3 shell. The temperature distribution along the self-heated nanowire is measured as a function of the applied electrical current, for both Joule and Peltier effects. An analysis is developed that is able to extract the thermal and thermoelectric properties including thermal conductivity, the thermal boundary resistance to the substrate and the Peltier coefficient from a single measurement. Our investigations demonstrate the potential of quantitative measurements of temperature around self-heated devices and structures down to the scattering length of heat carriers.

High-speed III-V nanowire photodetector monolithically integrated on Si.

Direct epitaxial growth of III-Vs on silicon for optical emitters and detectors is an elusive goal. Nanowires enable the local integration of high-quality III-V material, but advanced devices are hampered by their high-aspect ratio vertical geometry. Here, we demonstrate the in-plane monolithic integration of an InGaAs nanostructure p-i-n photodetector on Si. Using free space coupling, photodetectors demonstrate a spectral response from 1200-1700 nm. The 60 nm thin devices, with footprints as low as ~0.06 µm2, provide an ultra-low capacitance which is key for high-speed operation. We demonstrate high-speed optical data reception with a nanostructure photodetector at 32 Gb s-1, enabled by a 3 dB bandwidth exceeding ~25 GHz. When operated as light emitting diode, the p-i-n devices emit around 1600 nm, paving the way for future fully integrated optical links.

State dependence and temporal evolution of resistance in projected phase change memory.

Phase change memory (PCM) is being actively explored for in-memory computing and neuromorphic systems. The ability of a PCM device to store a continuum of resistance values can be exploited to realize arithmetic operations such as matrix-vector multiplications or to realize the synaptic efficacy in neural networks. However, the resistance variations arising from structural relaxation, 1/f noise, and changes in ambient temperature pose a key challenge. The recently proposed projected PCM concept helps to mitigate these resistance variations by decoupling the physical mechanism of resistance storage from the information-retrieval process. Even though the device concept has been proven successfully, a comprehensive understanding of the device behavior is still lacking. Here, we develop a device model that captures two key attributes, namely, resistance drift and the state dependence of resistance. The former refers to the temporal evolution of resistance, while the latter refers to the dependence of the device resistance on the phase configuration of the phase change material. The study provides significant insights into the role of interfacial resistance in these devices. The model is experimentally validated on projected PCM devices based on antimony and a metal nitride fabricated in a lateral device geometry and is also used to provide guidelines for material selection and device engineering.

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights.

Neuromorphic computing architectures enable the dense colocation of memory and processing elements within a single circuit. This colocation removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are nonvolatile synaptic elements such as memristors. Key memristor properties include a suitable nonvolatile resistance range, continuous linear resistance modulation, and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf0.57Zr0.43O2 (HZO) field-effect transistor (FeFET) with good linearity. Our FeFET operates with low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been performed over 4 bit depth with low noise (1%) in the tungsten oxide (WOx) readout channel. By adjusting the channel thickness from 15 to 8 nm, the on/off ratio of the FeFET can be engineered from 1 to 200% with an on-resistance ideally >100 kΩ, depending on the channel geometry. The device concept is using earth-abundant materials and is compatible with a back end of line (BEOL) integration into complementary metal-oxide-semiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high-density, large-scale integrated arrays of artificial analog synapses.

Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities.

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal⁻organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n⁺ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

Room-Temperature Lasing from Monolithically Integrated GaAs Microdisks on Silicon.

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever-increasing demand for more powerful computational systems. Monolithic III-V integration on Si promises to merge mature Si CMOS processing technology with III-V semiconductors possessing superior material properties, e. g., in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III-V optoelectronic devices in order to enable low-cost and power-efficient electronic-photonic integrated circuits. We report on room-temperature lasing from AlGaAs/GaAs microdisk cavities monolithically integrated on Si(001) using a selective epitaxial growth technique called template-assisted selective epitaxy. The grown gain material possesses high optical quality without indication of threading dislocations, antiphase boundaries, or twin defects. The devices exhibit single-mode lasing at T < 250 K and lasing thresholds between 2 and 18 pJ/pulse depending on the cavity size (1-3 µm in diameter).

Sub-10 Nanometer Feature Size in Silicon Using Thermal Scanning Probe Lithography.

High-resolution lithography often involves thin resist layers which pose a challenge for pattern characterization. Direct evidence that the pattern was well-defined and can be used for device fabrication is provided if a successful pattern transfer is demonstrated. In the case of thermal scanning probe lithography (t-SPL), highest resolutions are achieved for shallow patterns. In this work, we study the transfer reliability and the achievable resolution as a function of applied temperature and force. Pattern transfer was reliable if a pattern depth of more than 3 nm was reached and the walls between the patterned lines were slightly elevated. Using this geometry as a benchmark, we studied the formation of 10-20 nm half-pitch dense lines as a function of the applied force and temperature. We found that the best pattern geometry is obtained at a heater temperature of ∼600 °C, which is below or close to the transition from mechanical indentation to thermal evaporation. At this temperature, there still is considerable plastic deformation of the resist, which leads to a reduction of the pattern depth at tight pitch and therefore limits the achievable resolution. By optimizing patterning conditions, we achieved 11 nm half-pitch dense lines in the HM8006 transfer layer and 14 nm half-pitch dense lines and L-lines in silicon. For the 14 nm half-pitch lines in silicon, we measured a line edge roughness of 2.6 nm (3σ) and a feature size of the patterned walls of 7 nm.

Microstructure and ferroelectricity of BaTiO3 thin films on Si for integrated photonics.

Significant progress has been made in integrating novel materials into silicon photonic structures in order to extend the functionality of photonic circuits. One of these promising optical materials is BaTiO3 or barium titanate (BTO) that exhibits a very large Pockels coefficient as required for high-speed light modulators. However, all previous demonstrations show a noticable reduction of the Pockels effect in BTO thin films deposited on silicon substrates compared to BTO bulk crystals. Here, we report on the strong dependence of the Pockels effect in BTO thin films on their microstructure, and provide guidelines on how to engineer thin films with strong electro-optic response. We employ several deposition methods such as molecular beam epitaxy and chemical vapor deposition to realize BTO thin films with different morphology and crystalline structure. While a linear electro-optic response is present even in porous, polycrystalline BTO thin films with an effective Pockels coefficient r eff = 6 pm V-1, it is maximized for dense, tetragonal, epitaxial BTO films (r eff = 140 pm V-1). By identifying the key structural predictors of electro-optic response in BTO/Si, we provide a roadmap to fully exploit the linear electro-optic effect in novel hybrid oxide/semiconductor nanophotonic devices.