Simulation and Optimization Studies of the LHCb Beetle Readout ASIC and Machine Learning Approach for Pulse Shape Reconstruction.

The optimization of the Beetle readout ASIC and the performance of the software for the signal processing based on machine learning methods are presented. The Beetle readout chip was developed for the LHCb (Large Hadron Collider beauty) tracking detectors and was used in the VELO (Vertex Locator) during Run 1 and 2 of LHC data taking. The VELO, surrounding the LHC beam crossing region, was a leading part of the LHCb tracking system. The Beetle chip was used to read out the signal from silicon microstrips, integrating and amplifying it. The studies presented in this paper cover the optimization of its electronic configuration to achieve the lower power consumption footprint and the lower operational temperature of the sensors, while maintaining a good condition of the analogue response of the whole chip. The studies have shown that optimizing the operational temperature is possible and can be beneficial when the detector is highly irradiated. Even a single degree drop in silicon temperature can result in a significant reduction in the leakage current. Similar studies are being performed for the future silicon tracker, the Upstream Tracker (UT), which will start operating at LHC in 2021. It is expected that the inner part of the UT detector will suffer radiation damage similar to the most irradiated VELO sensors in Run 2. In the course of analysis we also developed a general approach for the pulse shape reconstruction using an ANN approach. This technique can be reused in case of any type of front-end readout chip.

The SALT-Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment.

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.