In-Materio Reservoir Computing in a Sulfonated Polyaniline Network.

A sulfonated polyaniline (SPAN) organic electrochemical network device (OEND) is fabricated using a simple drop-casting method on multiple Au electrodes for use in reservoir computing (RC). The SPAN network has humidity-dependent electrical properties. Under high humidity, the SPAN OEND exhibits mainly ionic conduction, including charging of an electric double layer and ionic diffusion. The nonlinearity and hysteresis of the current-voltage characteristics progressively increase with increasing humidity. The rich dynamic output behavior indicates wide variations for each electrode, which improves the RC performance because of the disordered network. For RC, waveform generation and short-term memory tasks are realized by a linear combination of outputs. The waveform task accuracy and memory capacity calculated from a short-term memory task reach 90% and 33.9, respectively. Improved spoken-digit classification is realized with 60% accuracy by only 12 outputs, demonstrating that the SPAN OEND can manage time series dynamic data operation in RC owing to a combination of rich dynamic and nonlinear electronic properties. The results suggest that SPAN-based electrochemical systems can be applied for material-based computing, by exploiting their intrinsic physicochemical behavior.

Mixed-precision weights network for field-programmable gate array.

In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {-1,1}, ternary {-1,0,1}, and 32-bit floating-point. We further developed the MPWN from both software and hardware aspects. From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets. We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight space combinations. From the hardware aspect, we proposed XOR signed-bits to explore floating-point and binary weight spaces in the MPWN. XOR signed-bits is an efficient implementation equivalent to multiplication of floating-point and binary weight spaces. Using the concept from XOR signed bits, we also provide a ternary bitwise operation that is an efficient implementation equivalent to the multiplication of floating-point and ternary weight space. To demonstrate the compatibility of the MPWN with hardware implementation, we synthesized and implemented the MPWN in a field-programmable gate array using high-level synthesis. Our proposed MPWN implementation utilized up to 1.68-4.89 times less hardware resources depending on the type of resources than a conventional 32-bit floating-point model. In addition, our implementation reduced the latency up to 31.55 times compared to 32-bit floating-point model without optimizations.

A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate.

In contrast to AI hardware, neuromorphic hardware is based on neuroscience, wherein constructing both spiking neurons and their dense and complex networks is essential to obtain intelligent abilities. However, the integration density of present neuromorphic devices is much less than that of human brains. In this report, we present molecular neuromorphic devices, composed of a dynamic and extremely dense network of single-walled carbon nanotubes (SWNTs) complexed with polyoxometalate (POM). We show experimentally that the SWNT/POM network generates spontaneous spikes and noise. We propose electron-cascading models of the network consisting of heterogeneous molecular junctions that yields results in good agreement with the experimental results. Rudimentary learning ability of the network is illustrated by introducing reservoir computing, which utilises spiking dynamics and a certain degree of network complexity. These results indicate the possibility that complex functional networks can be constructed using molecular devices, and contribute to the development of neuromorphic devices.

A shared synapse architecture for efficient FPGA implementation of autoencoders.

This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.